IR2175STRPBF Infineon

Data Sheet No. PD60208 Rev. E IR2175(S) & (PbF) LINEAR CURRENT SENSING IC Features Product Summary Floating channel up to +600V V 600Vmax Monolithic integration OFFSET Linear current feedback through shunt resistor I 2mA QBS Direct digital PWM output for easy interface Low IQBS allows the boot strap power supply V +/-260mVmax in Independent fast overcurrent trip signal o Gain temp.drift 20ppm/ C (typ.) High common mode noise immunity Input overvoltage protection for IGBT short circuit f 130kHz (typ.) condition o Open Drain outputs Overcurrent trip 2 sec (typ) Also available LEAD-FREE signal delay Description Overcurrent trip level +/-260mV (typ.) The IR2175 is a monolithic current sensing IC designed for motor drive applications. It senses the motor phase Packages current through an external shunt resistor, converts from analog to digital signal, and transfers the signal to the low side. IRs proprietary high voltage isolation tech- nology is implemented to enable the high bandwidth signal processing. The output format is discrete PWM to eliminate need for the A/D input interface for the IR2175. The dedicated overcurrent trip (OC) signal fa- cilitates IGBT short circuit protection. The open-drain outputs make easy for any interface from 3.3V to 15V. S 8 Lead PDIP 8 Lead SOIC IR2175 IR2175S Block Diagram Up to 600V 15V VCC V+ PWM Output PO VS IR2175 GND COM VB Overcurrent OC To Motor Phase (Refer to Lead Assignments for cor- rect pin configuration). This/These diagram(s) show electrical connec- tions only. Please refer to our Appli- cation Notes and DesignTips for proper circuit board layout.IR2175(S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side offset voltage -0.3 600 S V High side floating supply voltage -0.3 25 BS V Low side and logic fixed supply voltage -0.3 25 CC V V Maximum input voltage between V V -5 5 IN IN+ and S V Digital PWM output voltage COM -0.3 VCC +0.3 PO V Overcurrent output voltage COM -0.3 VCC +0.3 OC dV/dt Allowable offset voltage slew rate 50 V/ns P Package power dissipation T +25C 8 lead SOIC .625 D A W 8 lead PDIP 1.0 Rth Thermal resistance, junction to ambient 8 lead SOIC 200 JA C/W 8 lead PDIP 125 T Junction temperature 150 J C T Storage temperature -55 150 S T Lead temperature (soldering, 10 seconds) 300 L Note 1: Capacitors are required between VB and Vs when bootstrap power is used. The external power supply, when used, is required between VB and Vs pins. Recommended Operating Conditions The output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. Symbol Definition Min. Max. Units V High side floating supply voltage V +13.0 V +20 B S S V High side floating supply offset voltage 0.3 600 S V Digital PWM output voltage COM VCC PO V V Overcurrent output voltage COM VCC OC V Low side and logic fixed supply voltage 9.5 20 CC V Input voltage between V and V -260 +260 mV IN IN+ S T Ambient temperature -40 125 C A www.irf.com 2