IR2181SPBF Infineon

Data Sheet No. PD60172 Rev.G ( )( ) & (PbF) IR2181 4 S HIGH AND LOW SIDE DRIVER Packages Features Floating channel designed for bootstrap operation Fully operational to +600V 14-Lead PDIP Tolerant to negative transient voltage 8-Lead PDIP IR21814 IR2181 dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels 3.3V and 5V input logic compatible Matched propagation delay for both channels Logic and power ground +/- 5V offset. 14-Lead SOIC 8-Lead SOIC Lower di/dt gate driver for better noise immunity IR21814S IR2181S Output source/sink current capability 1.4A/1.8A Also available LEAD-FREE (PbF) IR2181/IR2183/IR2184 Feature Comparison Description % && The IR2181(4)(S) are high voltage, *7* high speed power MOSFET and IGBT % *7 % *7*9 % drivers with independent high and low *7: % < *7 % side referenced output channels. Pro- *7:9 =9 > % *79 prietary HVIC and latch immune % < 7 % *799 =9 > % CMOS technologies enable rugge- dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross- conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection IR2181 IR21814 (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1( ) ( ) & (PbF) IR2181 4 S Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side floating absolute voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V Low side and logic fixed supply voltage -0.3 25 CC V V Low side output voltage -0.3 V + 0.3 LO CC V Logic input voltage (HIN & LIN - IR2181/IR21814) V - 0.3 V + 5 IN SS SS V Logic ground (IR21814 only) V - 25 V + 0.3 SS CC CC dV /dt Allowable offset supply voltage transient 50 V/ns S P Package power dissipation T +25C (8-lead PDIP) 1.0 D A (8-lead SOIC) 0.625 W (14-lead PDIP) 1.6 (14-lead SOIC) 1.0 Rth Thermal resistance, junction to ambient (8-lead PDIP) 125 JA (8-lead SOIC) 200 C/W (14-lead PDIP) 75 (14-lead SOIC) 120 T Junction temperature 150 J T Storage temperature -50 150 S C T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V and V offset rating are tested with all supplies biased at 15V differential. S SS Symbol Definition Min. Max. Units VB High side floating supply absolute voltage V + 10 V + 20 S S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V Low side and logic fixed supply voltage 10 20 CC V V Low side output voltage 0 V LO CC V Logic input voltage (HIN & LIN - IR2181/IR21814) V V + 4 IN SS SS V Logic ground (IR21814/IR21824 only) -5 5 SS T Ambient temperature -40 125 C A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). Note 2: HIN and LIN pins are internally clamped with a 5.2V zener diode. 2 www.irf.com