IR2302SPBF Infineon

Data Sheet No. PD60207 Rev.A ( ) IR2302 S & (PbF) HALF-BRIDGE DRIVER Features Packages Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 5 to 20V 8-Lead SOIC Undervoltage lockout for both channels IR2302(S) (Also available LEAD-FREE (PbF)) 3.3V, 5V and 15V input logic compatible 8-Lead PDIP Cross-conduction prevention logic IR2302 Matched propagation delay for both channels High side output in phase with IN input 2106/2301//2108//2109/2302/2304 Feature Comparison Logic and power ground +/- 5V offset. Internal 540ns dead-time Lower di/dt gate driver for better noise immunity Shut down input turns off both channels % & 8-Lead SOIC also available LEAD-FREE (PbF). * 7 % 9 : 7 <7 & Description = 7 9 The IR2302(S) are high voltage, high speed : 7 <7 & power MOSFET and IGBT drivers with depen- % 9 dent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection & & & & > & % % IR2302 (Refer to Lead Assignments for correct configuration). This/ These diagram(s) show elec- trical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IR2302( ) S & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side floating absolute voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V V Low side and logic fixed supply voltage -0.3 25 CC V Low side output voltage -0.3 V + 0.3 LO CC V Logic input voltage (IN & SD) COM - 0.3 V + 0.3 IN CC dV /dt Allowable offset supply voltage transient 50 V/ns S P Package power dissipation T +25C (8 Lead PDIP) 1.0 D A W (8 Lead SOIC) 0.625 Rth Thermal resistance, junction to ambient (8 Lead PDIP) 125 JA C/W (8 Lead SOIC) 200 T Junction temperature 150 J T Storage temperature -50 150 S C T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units VB High side floating supply absolute voltage V + 5 V + 20 S S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V V Low side and logic fixed supply voltage 5 20 CC V Low side output voltage 0 V LO CC V Logic input voltage (IN & SD) COM V IN CC T Ambient temperature -40 150 C A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). 2 www.irf.com