IR2304STRPBF Infineon

Data Sheet No. PD60200 revB IR2304(S) & (PbF) HALF-BRIDGE DRIVER Features Product Summary Floating channel designed for bootstrap operation to +600V. Tolerant to negative transient voltage V 600V max. OFFSET dV/dt immune Gate drive supply range from 10 to 20V I +/- (min) 60 mA/130 mA O Under voltage lockout for both channels V 10 - 20V OUT 3.3V, 5V, and 15V input logic input compatible Delay Matching 50 ns Cross-conduction prevention logic Matched propagation delay for both channels Internal deadtime 100 ns Lower di/dt gate driver for better noise immunity ton/off (typ.) 220/220 ns Internal 100ns dead-time Output in phase with input Package Available in Lead-Free Description The IR2304(S) are a high voltage, high speed power MOSFET and IGBT driver with inde- 8 Lead SOIC 8-Lead PDIP pendent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies 2106/2301/2108/2109/2302/2304 Feature Comparison enable ruggedized monolithic construction. Cross- The logic input is compatible with standard Input conduction Part Dead-Time Ground Pins logic prevention CMOS or LSTTL output, down to 3.3V logic. logic The output driver features a high pulse cur- 2106/2301 COM HIN/LIN no none rent buffer stage designed for minimum driver 21064 VSS/COM cross-conduction. The floating channel can be 2108 Internal 540ns COM HIN/LIN yes 21084 Programmable 0.54~5 s VSS/COM used to drive an N-channel power MOSFET 2109/2302 Internal 540ns COM or IGBT in the high side configuration which IN/SD yes 21094 Programmable 0.54~5 s VSS/COM operates up to 600 volts. 2304 HIN/LIN yes Internal 100ns COM up to 600V Block Diagram Vcc HIN VB LIN LIN HO HIN TO VCC VS LOAD LO COM IR2304 www.irf.com 1IR2304(S)&(PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side offset voltage V - 25 V + 0.3 S B B V High side floating supply voltage -0.3 625 B V High side floating output voltage HO V - 0.3 V + 0.3 HO S B V Low side and logic fixed supply voltage -0.3 25 CC V V Low side output voltage LO -0.3 V + 0.3 LO CC V Logic input voltage (HIN, LIN) -0.3 V + 0.3 IN CC Com Logic ground V -25 V + 0.3 CC CC dV /dt Allowable offset voltage SLEW RATE 50 V/ns S P Package power dissipation T +25 C 8-Lead SOIC 0.625 D A W 8-Lead PDIP 1.0 Rth Thermal resistance, junction to ambient 8-Lead SOIC 200 JA C/W 8-Lead PDIP 125 T Junction temperature 150 J T Storage temperature -50 150 C S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units V High side floating supply voltage V + 10 V + 20 B S S V High side floating supply offset voltage Note 1 600 S V High side (HO) output voltage V V HO S B V V Low side (LO) output voltage COM V LO CC V Logic input voltage (HIN, LIN) COM V IN CC V Low side supply voltage 10 20 CC T Ambient temperature -40 125 C A Note 1: Logic operational for V of COM -5 to COM +600V. Logic state held for V of COM -5V to COM -V . S S BS 2 www.irf.com