IR3094MPBF Infineon

Data Sheet No. PD 94716 IR3094PBF 3 PHASE PWM CONTROLLER FOR POINT OF LOAD DESCRIPTION The IR3094 Control IC provides a full featured, cost effective, single chip solution to offers a compact, efficient solution for high current POL converters. Control and 3 Phase Gate Drive functions are integrated into a single space-saving IC. FEATURES x 0.85V Reference Voltage x 3A GATELX Pull Down Drive Capability x Programmable 100KHz to 540KHz oscillator x Programmable Voltage Positioning (can be disabled) x Programmable Softstart x Programmable Hiccup Over-Current Protection with Delay to prevent false triggering x Simplified Powergood provides indication of proper operation and avoids false triggering x Operates up to 16V converter input with 7.5V Under-Voltage Lockout x 4.36V Under-Voltage Lockout threshold for gate driver voltage x Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage x Enable Input x OVP Flag Output detects high side fet short at powerup x Separate OVP sense line to sense the output voltage and latched OVP with protection x Inductor DCR sensing for current sensing will support up to 5.1V output applications x Available 48L MLPQ package ORDERING INFORMATION Device Order Quantity IR3094MTRPBF 3000 per Reel IR3094MPBF 100 piece strips PACKAGE INFORMATION NC GATEH1 N C PGND1 48L MLPQ ROSC GATEL1 (7 x 7 mm Body) VOSNS- VCCL1 2 IR3094 OCSET 5VUVL o = 27 C/W JA VREF GATEL2 48LD MLPQ VDRP PGND2 FB GATEH2 EAOUT VCCH2 SS/DEL VCCH3 SCOMP2 GATEH3 SCOMP3 PGND3 Page 1 of 29 09/26/05 LGND NC SETBIAS NC VCC NC CSINP3 NC CSINM3 5VREF BIASOUT OVPSNS ENABLE PWRGD CSINP2 OVP CSINP1 CSINM2 NC CSINM1 VCCL3 NC GATEL3 VCCH1 IR3094PBF PIN DESCRIPTION PIN PIN SYMBOL PIN DESCRIPTION 1 NC Not connected 2 NC Not connected 3 ROSC Connect a resistor to VOSNS- to program oscillator frequency, OCSET and STBIAS bias currents. 4 VOSNS- Remote Sense Input. Connect to ground at the load. Programs the hiccup over-current threshold through an external resistor tied to VREF and an internal current 5 OCSET source. The bias current is a function of ROSC. 0.85V Reference voltage. Current Sensing and Over Current Protection are referenced to this pin. An 6 VREF external RC network tied to VOSNS- is needed for the compensation. Buffered average current information. Connect an external resistor to FB to program converter output. 7 VDRP .impedance 8 FB Inverting input to the Error Amplifier. 9 EAOUT Output of the Error Amplifier. Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to 10 SS/DEL LGND to program the timing. Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loops 11 SCOMP2 bandwidth. Phase 2 is forced to match phase 1s current. Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loops 12 SCOMP3 bandwidth. Phase 3 is forced to match phase 1s current. 13 LGND Local Ground and IC substrate connection. 14 SETBIAS External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC. 15 VCC Power for internal circuitry and source for BIASOUT regulator. 16 CSINP3 Non-inverting input to the Phase 3 Current Sense Amplifier. 17 CSINM3 Inverting input to the Phase 3 Current Sense Amplifier. 18 BIASOUT 150mA open-looped regulated voltage set by SETBIAS for GATE drive bias. 19 PWRGD Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up. 20 CSINP2 Non-inverting input to the Phase 2 Current Sense Amplifier. 21 CSINM2 Inverting input to the Phase 2 Current Sense Amplifier. 22 NC Not connected 23 VCCL3 Power for Phase 3 Low-Side Gate Driver. 24 GATEL3 Phase 3 Low-Side Gate Driver Output and input to GATEH3 non-overlap comparator. 25 PGND3 Return for Phase 3 Gate Drivers. 26 GATEH3 Phase 3 High-Side Gate Driver Output and input to GATEL3 non-overlap comparator. 27 VCCH3 Power for Phase 3 High-Side Gate Driver. 28 VCCH2 Power for Phase 2 High-Side Gate Driver. 29 GATEH2 Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator. 30 PGND2 Return for Phase 2 Gate Drivers. 31 GATEL2 Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator. Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under 32 5VUVL voltage condition initiates Soft Start. 33 VCCL1 2 Power for Phase 1 and 2 Low-Side Gate Drivers. 34 GATEL1 Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator. 35 PGND1 Return for Phase 1 Gate Drivers. 36 GATEH1 Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator. 37 VCCH1 Power for Phase 1 High-Side Gate Driver. 38 NC Not connected 39 CSINM1 Inverting input to the Phase 1 Current Sense Amplifier. 40 CSINP1 Non-inverting input to the Current Sense Amplifier. 41 OVP Output that drives high during an Over-Voltage condition. 42 ENABLE Enable Input. A logic low applied to this pin puts the IC into Fault mode. 43 OVPSNS Dedicated output voltage sense pin for Over Voltage Protection. 44 5VREF Decoupling for internal voltage reference rail. 45 NC Not connected 46 NC Not connected 47 NC Not connected 48 NC Not connected Page 2 of 29 09/26/05