Data Sheet No.PD60229 revB IR5001S & (PbF) UNIVERSAL ACTIVE ORING CONTROLLER FEATURES DESCRIPTION The IR5001S is a universal high-speed controller and Controller / driver IC in an SO-8 package for N-channel power MOSFET driver for Active ORing and implementation of Active ORing / reverse polarity reverse polarity protection applications. The output voltage protection using N-channel Power MOSFETs of the IR5001S is determined based on the polarity of the Suitable for both input ORing (for carrier class voltage difference on its input terminals. In particular, if the telecom equipment) as well as output ORing for current flow through an N-channel ORing FET is from redundant DC-DC and AC-DC power supplies source to drain, the output of the IR5001S will be pulled 130ns Typical Turn-Off delay time high to Vcc, thus turning the Active ORing FET on. If the 3A Peak Turn-Off gate drive current current reverses direction and flows from drain to source Asymmetrical offset voltage of the internal high-speed (due to a short-circuit failure of the source, for example), comparator prevents potential oscillations at light load the IC will quickly switch the Active ORing FET off. Typical Ability to withstand continuous gate short conditions turn-off delay for the IR5001S is only 130nS, which helps Integrated voltage clamps on both comparator inputs to minimize voltage sags on the redundant dc voltage. allow continuous application of up to 100V Both inputs to the IC (INN and INP) as well as Vline Option to be powered either directly from 36-75V input contain integrated high voltage resistors and internal universal telecom bus (100V max), or from an clamps. This makes the IR5001S suitable for applications external bias supply and bias resistor at voltages up to 100V, and with a minimum number of Input/Output pins to determine the state of the Active external components. ORing circuit and power system redundancy APPLICATIONS TYPICAL APPLICATION -48V/-24V Input Active ORing for carrier +48V input A class communication equipment B IR5001 Reverse input polarity protection for Vline Vout DC-DC power supplies DC Vcc Gnd 24V/48V output active ORing for DC INN FETch redundant AC-DC rectifiers FET Check Pulse Low output voltage (12V, 5V, 3.3V...) FET A Status FETst INP active ORing for redundant DC-DC and AC-DC power supplies Active ORing of multiple voltage -48V input A regulators for redundant processor IR5001 power Vline Vout Vcc Gnd FETch INN Fet B Status FETst INP -48V input B F 1 - Typical application of the IR5001S in - 48V input, carrier class telecommunications equipment. Top View PACKAGE / ORDERING INFORMATION Vline 1 8 Vout Vcc 2 7 Gnd PKG PART LEADFREE PIN PARTS PARTS T & R 3 6 INN FETch FETst 4 5 DESIG. NUMBER PART NUMBER COUNT PER TUBE PER REEL Oriantation INP S IR5001S IR5001SPbF 8 95 ------ Fig A JA=128C/W S IR5001STR IR5001STRPbF 8 ------- 2500 www.irf.com 1IR5001S & (PbF) ABSOLUTE MAXIMUM RATINGS Vline Voltage -5.0V to 100V (continuous) Vcc Voltage -0.5V to 15VDC Icc Current 5mA INN, INP Voltage -5.0V to 100V (continuous) FETch, FETst -0.5V to 5.5V FETst Sink Current 10mA Junction Temperature -40C to 125C Storage Temperature Range -65C to 150C CAUTION: 1. Stresses above those listed inAbsolute Maximum Rating may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. 2. This device is ESD sensitive. Use of standard ESD handling precautions is required ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vline = 36V to 100V Vcc is decoupled with 0.1uF to Gnd, CL=10nF at Vout INP is connected to Gnd. Typical values refer to TA=25C. Minimum and maximum limits apply to TA= 0C to 85C temperature range and are 100% production-tested at both temperature extremes. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETERS SYMBOL TEST CONDITION MIN TYP MAX UNITS Vline=25V 0.14 0.3 0.5 Bias Section Iline Vline=36V 0.2 0.5 0.75 mA Vline Bias Current Vline=100V, Note 1 1.2 1.7 2.2 VCC output voltage Vcc(out) Vline=25V 10.2 12.5 14.1 V Vline=open, VINP=0 VINN= - 0.3V UVLO Section Vcc(ON) 8.0 9.6 10.7 UVLO ON Threshold Voltage Vcc increased until Vout switches from LO to HI, Note 2 V Vline=open, VINP=0, VINN=- UVLO OFF Threshold Voltage Vcc(OFF) 0.3V, Vcc is decreased until 5.6 7.2 8.8 Vout switches from HI to LO UVLO Hysteresis 1.6 2.3 2.8 V VINP=0V and VINN Ramping up, Input Comparator Section Input Offset Voltage (VINP- Vos VOUT changes from HI to LO, -7.9 -4.0 0 VINN) Fig.3 mV VINP=0,VINN ramping down, Input Hysteresis Voltage Vhyst 13 31 44 Figures 3 and 4 (INN) Input Bias Current I(INN) VINP=0V, VINN=36V 0.2 0.5 0.9 mA (INP) Input Bias Current I(INP) VINN=0V, VINP=36V 0.2 0.5 0.9 www.irf.com 2