IRS2004SPBF Infineon

Data Sheet No.PD60270 IRS2004(S)PbF HALF-BRIDGE DRIVER Features Product Summary Floating channel designed for bootstrap operation V 200 V max. OFFSET Fully operational to +200 V Tolerant to negative transient voltage, dV/dt I +/- 130 mA/270 mA O immune Gate drive supply range from 10 V to 20 V V 10 V - 20 V OUT Undervoltage lockout 3.3 V, 5 V, and 15 V input logic compatible t (typ.) 680 ns/150 ns on/off Cross-conduction prevention logic Internally set deadtime Deadtime (typ.) 520 ns High-side output in phase with input Shutdown input turns off both channels Packages Matched propagation delay for both channels RoHS compliant Description The IRS2004 is a high voltage, high speed power MOSFET and IGBT driver with dependent high- and low- side referenced output channels. Proprietary HVIC and 8 Lead SOIC 8 Lead PDIP latch immune CMOS technologies enable ruggedized IRS2004S IRS2004 monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross- conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates from 10 V to 200 V. Typical Connection (Refer to Lead Assignment for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IRS2004(S) PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High-side floating absolute voltage -0.3 225 B V High-side floating supply offset voltage V - 25 V + 0.3 S B B V High-side floating output voltage V - 0.3 V + 0.3 HO S B V V Low-side and logic fixed supply voltage -0.3 25 CC V Low-side output voltage -0.3 V + 0.3 LO CC V Logic input voltage (IN & )-0.3V + 0.3 IN CC dV /dt Allowable offset supply voltage transient 50 V/ns s (8 lead PDIP) 1.0 P Package power dissipation T +25 C D A W (8 lead SOIC) 0.625 (8 lead PDIP) 125 C/W Rth Thermal resistance, junction to ambient JA (8 lead SOIC) 200 T Junction temperature 150 J C T Storage temperature -55 150 S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at a 15 V differential. S Symbol Definition Min. Max. Units V High-side floating supply absolute voltage V + 10 V + 20 B S S V High-side floating supply offset voltage Note 2 200 S V High-side floating output voltage V V HO S B V V Low-side and logic fixed supply voltage 10 20 CC V Low-side output voltage 0 V LO CC V Logic input voltage (IN & )0V IN CC C T Ambient temperature -40 125 A Note 1: Logic operational for V of -5 V to +200 V. Logic state held for V of -5 V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). www.irf.com 2