IRS21064STRPBF Infineon

Data Sheet No. PD60246 IRS2106/IRS21064(S)PbF HIGH AND LOW SIDE DRIVER Features Packages Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune 8-Lead PDIP Gate drive supply range from 10 V to 20 V 14-Lead PDIP Undervoltage lockout for both channels 3.3 V, 5 V, and 15 V input logic compatible Matched propagation delay for both channels 14-Lead PDIP Logic and power ground +/- 5 V offset Lower di/dt gate driver for better noise immunity Outputs in phase with inputs (IRS2106) RoHS compliant 14-Lead SOIC 8-Lead SOIC Description Feature Comparison The IRS2106/IRS21064 are high Cross- voltage, high speed power MOSFET Input Deadtime t /t conduction on off Part Ground Pins and IGBT drivers with independent logic prevention (ns) (ns) logic high- and low-side referenced output 2106/2301 COM HIN/LIN no none 220/200 channels. Proprietary HVIC and 21064 VSS/COM latch immune CMOS technologies 2108 Internal 540 COM HIN/LIN yes 220/200 21084 Programmable 540 - 5000 VSS/COM enable ruggedized monolithic con- 2109/2302 Internal 540 COM IN/SD yes 750/200 struction. The logic input is 21094 Programmable 540 - 5000 VSS/COM compatible with standard CMOS or HIN/LIN yes Internal 100 160/140 2304 COM LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 V. up to 600 V Typical Connection V CC V V CC B HIN HIN HO LIN TO LIN V S LOAD COM LO up to 600 V IRS2106 HO V V V CC B CC HIN V HIN S TO LIN LOAD LIN (Refer to Lead Assignments for correct pin IRS21064 configuration). These diagrams show electri- cal connections only. Please refer to our V COM V SS SS Application Notes and DesignTips for proper LO circuit board layout. www.irf.com 1IRS2106/IRS21064(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High-side floating absolute voltage -0.3 625 B V High-side floating supply offset voltage V - 25 V + 0.3 S B B V High-side floating output voltage V - 0.3 V + 0.3 HO S B V Low-side and logic fixed supply voltage -0.3 25 CC V V Low-side output voltage -0.3 V + 0.3 LO CC V Logic input voltage V - 0.3 V + 0.3 IN SS CC V Logic ground (IRS21064 only) V - 25 V + 0.3 SS CC CC dV /dt Allowable offset supply voltage transient 50 V/ns S (8 lead PDIP) 1.0 (8 lead SOIC) 0.625 P Package power dissipation T +25 C D A W (14 lead PDIP) 1.6 (14 lead SOIC) 1.0 (8 lead PDIP) 125 (8 lead SOIC) 200 Rth Thermal resistance, junction to ambient JA C/W (14 lead PDIP) 75 (14 lead SOIC) 120 T Junction temperature 150 J T Storage temperature -50 150 S C T Lead temperature (soldering, 10 seconds) 300 L www.irf.com 2