Data Sheet No. PD60260 / IRS2108 IRS21084(S)PbF HALF-BRIDGE DRIVER Features Floating channel designed for bootstrap operation Packages Fully operational to +600 V Tolerant to negative transient voltage, dV/dt 8-Lead PDIP immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 14-Lead PDIP 3.3 V, 5 V, and 15 V input logic compatible Cross-conduction prevention logic Matched propagation delay for both channels High-side output in phase with HIN input Low-side output out of phase with input Logic and power ground +/- 5 V offset Internal 540 ns deadtime, and programmable up 8-Lead SOIC 14-Lead SOIC to 5 s with one external R resistor (IRS21084) DT Lower di/dt gate driver for better noise immunity RoHS compliant Description Feature Comparison The IRS2108/IRS21084 are high volt- age, high speed power MOSFET and t /t on off IGBT drivers with dependent high- and % & % & low-side referenced output channels. 9: *9 : * 99 *9 Proprietary HVIC and latch immune 9: < * CMOS technologies enable ruggedized 9: = >< * 99 *9 9: =< >< > * monolithic construction. The logic input 9: A*9 9 >< * J> *9 is compatible with standard CMOS or >< > 9: A< * LSTTL output, down to 3.3 V logic. The : *:< 9 < * : output drivers feature a high pulse cur- rent buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. Typical Connection IRS21084 IRS2108 (Refer to Lead Assignments for correct pin configuration). These diagrams show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IRS2108/IRS21084(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High-side floating absolute voltage -0.3 625 B V High-side floating supply offset voltage V - 25 V + 0.3 S B B V High-side floating output voltage V - 0.3 V + 0.3 HO S B V Low-side and logic fixed supply voltage -0.3 25 CC V V Low-side output voltage -0.3 V + 0.3 LO CC DT Programmable deadtime pin voltage (IRS21084 only) V - 0.3 V + 0.3 SS CC V Logic input voltage (HIN & )V - 0.3 V + 0.3 IN SS CC V Logic ground (IRS21084 only) V - 25 V + 0.3 SS CC CC dV /dt Allowable offset supply voltage transient 50 V/ns S (8 lead PDIP) 1.0 (8 lead SOIC) 0.625 o P Package power dissipation TA +25 C D W (14 lead PDIP) 1.6 (14 lead SOIC) 1.0 (8 lead PDIP) 125 (8 lead SOIC) 200 R Thermal resistance, junction to ambient thJA (14 lead PDIP) 75 C/W (14 lead SOIC) 120 T Junction temperature 150 J T Storage temperature -50 150 C S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V and V offset rating are tested with all supplies biased at a 15 V differential. S SS Symbol Definition Min. Max. Units VB High-side floating supply absolute voltage V + 10 V + 20 S S V High-side floating supply offset voltage Note 1 600 S V High-side floating output voltage V V HO S B V Low-side and logic fixed supply voltage 10 20 CC V Low-side output voltage 0 V LO CC V IRS2108 COM V CC V Logic input voltage IN IRS21084 V V SS CC DT Programmable deadtime pin voltage (IRS21084 only) V V S CC V Logic ground (IRS21084 only) -5 5 SS T Ambient temperature -40 125 C A Note 1: Logic operational for V of -5 V to +600 V. Logic state held for V of -5 V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). www.irf.com 2