Data Sheet No. PD60249 IRS2110(-1,-2,S)PbF IRS2113(-1,-2,S)PbF HIGH AND LOW SIDE DRIVER Features Product Summary Floating channel designed for bootstrap operation Fully operational to +500 V or +600 V V (IRS2110) 500 V max. OFFSET Tolerant to negative transient voltage, dV/dt immune (IRS2113) 600 V max. Gate drive supply range from 10 V to 20 V I +/- 2 A/2 A O Undervoltage lockout for both channels 3.3 V logic compatible V 10 V - 20 V OUT Separate logic supply range from 3.3 V to 20 V t (typ.) 130 ns & 120 ns on/off Logic and power ground 5V offset CMOS Schmitt-triggered inputs with pull-down Delay Matching (IRS2110) 10 ns max. Cycle by cycle edge-triggered shutdown logic (IRS2113) 20 ns max. Matched propagation delay for both channels Packages Outputs in phase with inputs RoHS compliant Description The IRS2110/IRS2113 are high voltage, high speed power MOSFET and IGBT drivers with independent high-side and low-side referenced output channels. Pro- 16-Lead PDIP 14-Lead PDIP prietary HVIC and latch immune CMOS technologies (w/o leads 4 & 5) IRS2110 and IRS2113 enable ruggedized monolithic construction. Logic in- IRS2110-2 and IRS2113-2 puts are compatible with standard CMOS or LSTTL out- put, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel 16-Lead SOIC 14-Lead PDIP IRS2110S and power MOSFET or IGBT in the high-side configuration (w/o lead 4) IRS2113S IRS2110-1 and IRS2113-1 which operates up to 500 V or 600 V. up to 500 V or 600 V Typical Connection HO V V V DD DD B HIN V HIN S TO LOAD SD SD LIN LIN V CC V COM V SS SS V LO CC (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connec- tions only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IRS2110(-1,-2,S)PbF/IRS2113(-1,-2,S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35. Symbol Definition Min. Max. Units (IRS2110) -0.3 520 (Note 1) V B High-side floating supply voltage (IRS2113) -0.3 620 (Note 1) V High-side floating supply offset voltage V - 20 V + 0.3 S B B V High-side floating output voltage V - 0.3 V + 0.3 HO S B V Low-side fixed supply voltage -0.3 20 (Note 1) CC V V Low-side output voltage -0.3 V + 0.3 LO CC V +20 SS V Logic supply voltage -0.3 DD (Note 1) V Logic supply offset voltage V - 20 V + 0.3 SS CC CC V Logic input voltage (HIN, LIN, & SD) V - 0.3 V + 0.3 IN SS DD dV /dt Allowable offset supply voltage transient (Fig. 2) 50 V/ns s (14 lead DIP) 1.6 W PD Package power dissipation TA +25 C (16 lead SOIC) 1.25 (14 lead DIP) 75 RTHJA Thermal resistance, junction to ambient C/W (16 lead SOIC) 100 T Junction temperature 150 J C T Storage temperature -55 150 S T Lead temperature (soldering, 10 seconds) 300 L Note 1: All supplies are fully tested at 25 V, and an internal 20 V clamp exists for each supply. Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the recommended conditions. The V and V offset ratings are tested with all supplies biased at a 15 V differential. S SS Typical ratings at other bias conditions are shown in Figs. 36 and 37. Symbol Definition Min. Max. Units V High-side floating supply absolute voltage V + 10 V + 20 B S S (IRS2110) Note 2 500 VS High-side floating supply offset voltage (IRS2113) Note 2 600 V High-side floating output voltage V V HO S B V Low-side fixed supply voltage 10 20 CC V V Low-side output voltage 0 VCC LO V Logic supply voltage V + 3 V + 20 DD SS SS V Logic supply offset voltage -5 (Note 3) 5 SS V Logic input voltage (HIN, LIN & SD) V V IN SS DD T Ambient temperature -40 125 C A Note 2: Logic operational for V of -4 V to +500 V. Logic state held for V of -4 V to -V . (Refer to the Design Tip DT97-3) S S BS Note 3: When V < 5 V, the minimum V offset is limited to -V DD SS DD. www.irf.com 2