Data Sheet No. PD60251 ( ) IRS2112 -1,-2,S PbF HIGH AND LOW SIDE DRIVER Features Product Summary Floating channel designed for bootstrap operation Fully operational to +600 V V 600 V max. Tolerant to negative transient voltage, dV/dt OFFSET immune I +/- 200 mA / 440 mA Gate drive supply range from 10 V to 20 V O Undervoltage lockout for both channels 3.3 V logic compatible V 10 V - 20 V OUT Separate logic supply range from 3.3 V to 20 V Logic and power ground +/- 5 V offset t (typ.) 135 ns & 105 ns on/off CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Delay Matching 30 ns Matched propagation delay for both channels Outputs in phase with inputs Packages RoHS compliant 14-Lead PDIP Description IRS2112 The IRS2112 is a high voltage, high speed power 16-Lead PDIP MOSFET and IGBT driver with independent high- and (w/o leads 4 & 5) IRS2112-2 low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable rug- 14-Lead PDIP gedized monolithic construction. Logic inputs are com- (w/o lead 4) patible with standard CMOS or LSTTL outputs, down IRS2112-1 to 3.3 V logic. The output drivers feature a high pulse 16-Lead SOIC current buffer stage designed for minimum driver IRS2112S cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. up to 600 V Typical Connection HO V V V DD DD B HIN HIN V S TO LOAD SD SD LIN V LIN CC V COM V SS SS V LO CC (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IRS2112(-1,-2,S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35. Symbol Definition Min. Max. Units V High-side floating supply voltage -0.3 625 B V High-side floating supply offset voltage V - 25 V + 0.3 S B B V High-side floating output voltage V - 0.3 V + 0.3 HO S B V Low-side fixed supply voltage -0.3 25 CC V V Low-side output voltage -0.3 V + 0.3 LO CC V Logic supply voltage -0.3 V + 25 DD SS V Logic supply offset voltage V - 25 V + 0.3 SS CC CC V Logic input voltage (HIN, LIN & SD) V - 0.3 V + 0.3 IN SS DD dV /dt Allowable offset supply voltage transient (Fig. 2) 50 V/ns s (14 Lead DIP) 1.6 W P Package power dissipation TA +25 C D (16 Lead SOIC) 1.25 (14 Lead DIP) 75 C/W RTH Thermal resistance, junction to ambient JA (16 Lead SOIC) 100 T Junction temperature 150 J C T Storage temperature -55 150 S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V and V offset ratings are tested with all supplies biased at 15 V differential. Typical S SS ratings at other bias conditions are shown in Figs. 36 and 37. Symbol Definition Min. Max. Units V High-side floating supply absolute voltage V + 10 V + 20 B S S V High-side floating supply offset voltage Note 1 600 S V High-side floating output voltage V V HO S B V Low-side fixed supply voltage 10 20 CC V V Low-side output voltage 0 V LO CC V Logic supply voltage V + 3 V + 20 DD SS SS V Logic supply offset voltage -5 (Note 2) 5 SS V Logic input voltage (HIN, LIN & SD) V V IN SS DD T Ambient temperature -40 125 C A Note 1: Logic operational for V of -5 V to +600 V. Logic state held for V of -5 V to -V . (Please refer to the Design S S BS Tip DT97-3 for more details). Note 2: When V < 5 V, the minimum V offset is limited to -V . DD SS DD www.irf.com 2 PDF created with pdfFactory trial version www.pdffactory.com