Data Sheet No. PD60238 revE IRS2153(1)D(S)PbF SELF-OSCILLATING HALF-BRIDGE DRIVER IC Features Product Summary Integrated 600 V half-bridge gate driver V 600 V Max OFFSET C , R programmable oscillator T T 15.4 V Zener clamp on V CC Micropower startup Duty cycle 50% Non-latched shutdown on C pin (1/6th V ) T CC Driver source/sink Internal bootstrap FET 180 mA/260 mA typ. current Excellent latch immunity on all inputs and outputs +/- 50 V/ns dV/dt immunity V 15.4 V typ. clamp ESD protection on all pins 8-lead SOIC or PDIP package 1.1 s typ. (IRS2153D) Deadtime Internal deadtime 0.6 s typ. (IRS21531D) Description Package The IRS2153(1)D is based on the popular IR2153 self- oscillating half-bridge gate driver IC using a more advanced silicon platform, and incorporates a high voltage half-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer. HVIC and latch immune CMOS technologies enable rugged monolithic construction. The output driver features a high PDIP8 SO8 pulse current buffer stage designed for minimum driver IRS2153(1)DPbF IRS2153(1)DSPbF cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers. Typical Connection Diagram + AC Rectified Line RVCC VCC VB 8 1 CBOOT MHS RT HO 2 7 RT L CT VS 3 6 CVCC CT RL MLS COM LO 4 5 - AC Rectified Line 1 IRS2153(1)D IRS2153(1)D Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Parameter Symbol Definition Min. Max. Units V B High side floating supply voltage -0.3 625 V High side floating supply offset voltage V - 25 V + 0.3 S B B V V High side floating output voltage V 0.3 V + 0.3 HO S B V Low side output voltage -0.3 V + 0.3 LO CC I R pin current -5 5 mA RT T V R pin voltage -0.3 V + 0.3 RT T CC V V C pin voltage -0.3 V + 0.3 CT T CC I CC Supply current (Note 1) --- 20 mA Maximum allowable current at LO and HO due to external I -500 500 OMAX power transistor Miller effect. Allowable offset voltage slew rate -50 50 V/ns dV /dt S P Maximum power dissipation T +25 C, 8-Pin DIP --- 1.0 D A W P Maximum power dissipation T +25 C, 8-Pin SOIC --- 0.625 D A R Thermal resistance, junction to ambient, 8-Pin DIP --- 85 thJA C/W R Thermal resistance, junction to ambient, 8-Pin SOIC --- 128 thJA T J Junction temperature -55 150 T Storage temperature -55 150 C S T Lead temperature (soldering, 10 seconds) --- 300 L Note 1: This IC contains a zener clamp structure between the chip V and COM which has a nominal CC breakdown voltage of 15.4 V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the V specified in the Electrical Characteristics section. CLAMP 2