IRS2184SPBF Infineon

Data Sheet No. PD60252 revA / IRS2184 IRS21844(S)PbF HALF-BRIDGE DRIVER Features Packages Floating channel designed for bootstrap operation 8-Lead PDIP Fully operational to +600 V IRS2184 Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V 14-Lead PDIP Undervoltage lockout for both channels IRS21844 3.3 V and 5 V input logic compatible Matched propagation delay for both channels Logic and power ground +/- 5 V offset 14-Lead SOIC Lower di/dt gate driver for better noise immunity IRS21844S Output source/sink current capability 1.4 A/1.8 A RoHS compliant 8-Lead SOIC IRS2184S Description The IRS2184/IRS21844 are high volt- Feature Comparison age, high speed power MOSFET and Cross- IGBT drivers with dependent high- and Input conduction Deadtime t /t on off Part Ground Pins low-side referenced output channels. logic prevention (ns) (ns) logic Proprietary HVIC and latch immune 2181 COM CMOS technologies enable ruggedized HIN/LIN no none 180/220 21814 VSS/COM monolithic construction. The logic in- 2183 Internal 400 COM HIN/LIN yes 180/220 21834 Program 400-5000 VSS/COM put is compatible with standard CMOS 2184 Internal 400 COM IN/SD yes 680/270 or LSTTL output, down to 3.3 V logic. The 21844 Program 400-5000 VSS/COM output drivers feature a high pulse cur- rent buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. Typical Connection up to 600 V V CC V V CC B IN IN HO SD TO SD V S LOAD COM LO up to 600 V IRS2184 HO IRS21844 V V V CC CC B IN V IN S TO LOAD SD SD (Refer to Lead Assignments for correct DT configuration).These diagrams show V V COM SS SS electrical connections only. Please refer R DT LO to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 PDF created with pdfFactory trial version www.pdffactory.comIRS2184/IRS21844(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High-side floating absolute voltage -0.3 620 (Note 1) B V High-side floating supply offset voltage V - 20 V + 0.3 S B B V High-side floating output voltage V - 0.3 V + 0.3 HO S B V Low-side and logic fixed supply voltage -0.3 20 (Note 1) CC V V Low-side output voltage -0.3 V + 0.3 LO CC DT Programmable dead-time pin voltage (IRS21844 only) V - 0.3 V + 0.3 SS CC V Logic input voltage (IN & SD) V - 0.3 V + 0.3 IN SS CC V Logic ground (IRS21844 only) V - 20 V + 0.3 SS CC CC dV /dt Allowable offset supply voltage transient 50 V/ns S (8-lead PDIP) 1.0 (8-lead SOIC) 0.625 P Package power dissipation T +25 C D A W (14-lead PDIP) 1.6 (14-lead SOIC) 1.0 (8-lead PDIP) 125 (8-lead SOIC) 200 RthJ Thermal resistance, junction to ambient A C/W (14-lead PDIP) 75 (14-lead SOIC) 120 T Junction temperature 150 J T Storage temperature -50 150 C S T Lead temperature (soldering, 10 seconds) 300 L Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply. www.irf.com 2 PDF created with pdfFactory trial version www.pdffactory.com