Data Sheet No. PD60277 IRS2304(S)PbF HALF-BRIDGE DRIVER Features Floating channel designed for bootstrap operation Product Summary to +600 V Tolerant to negative transient voltage, dV/dt V 600 V max. OFFSET immune Gate drive supply range from 10 V to 20 V I +/- (min) 60 mA/130 mA O Undervoltage lockout for both channels V 10 V - 20 V OUT 3.3 V, 5 V, and 15 V input logic input compatible Delay Matching 50 ns Cross-conduction prevention logic Matched propagation delay for both channels Internal deadtime 100 ns Lower di/dt gate driver for better noise immunity ton/off (typ.) 150 ns/150 ns Internal 100 ns deadtime Output in phase with input Package RoHS compliant Description 8-Lead 8 Lead The IRS2304 is a high voltage, high speed power PDIP SOIC MOSFET and IGBT driver with independent high-side and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Feature Comparison The logic input is compatible with Cross- standard CMOS or LSTTL output, Input conduction Deadtime t /t on off down to 3.3 V logic. The output driver Part Ground Pins logic prevention (ns) (ns) features a high pulse current buffer logic 2106/2301 COM stage designed for minimum driver HIN/LIN no none 220/200 21064 VSS/COM cross-conduction. The floating chan- 2108 Internal 540 COM HIN/LIN yes 220/200 nel can be used to drive an N-chan- Programmable 540 - 5000 21084 VSS/COM nel power MOSFET or IGBT in the 2109/2302 Internal 540 COM IN/SD yes 750/200 Programmable 540 - 5000 high-side configuration which oper- 21094 VSS/COM HIN/LIN yes Internal 100 160/140 ates up to 600 V. 2304 COM up to 600 V Block Diagram Vcc LIN LIN VB HIN HO HIN VCC TO VS LOAD COM LO (Refer to Lead Assignments for cor- rect pin configuration). These dia- grams show electrical connections only. Please refer to our Application Notes and DesignTips for proper cir- cuit board layout. www.irf.com 1 PDF created with pdfFactory trial version www.pdffactory.comIRS2304(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High-side offset voltage V - 25 V + 0.3 S B B V High-side floating supply voltage -0.3 625 B V High-side floating output voltage HO V - 0.3 V + 0.3 HO S B V Low-side and logic fixed supply voltage -0.3 25 CC V V Low-side output voltage LO -0.3 V + 0.3 LO CC V Logic input voltage (HIN, LIN) -0.3 V + 0.3 IN CC Com Logic ground V -25 V + 0.3 CC CC dV /dt Allowable offset supply voltage transient 50 V/ns S 8-Lead SOIC 0.625 P Package power dissipation TA +25 C W D 8-Lead PDIP 1.0 8-Lead SOIC 200 Rth Thermal resistance, junction to ambient C/W JA 8-Lead PDIP 125 T Junction temperature 150 J T Storage temperature -50 150 C S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15 V differential. S Symbol Definition Min. Max. Units V High-side floating supply voltage V + 10 V + 20 B S S V High- side floating supply offset voltage Note 1 600 S V High-side (HO) output voltage V V HO S B V V Low-side (LO) output voltage COM V LO CC V Logic input voltage (HIN, LIN) COM V IN CC V Low- side supply voltage 10 20 CC T Ambient temperature -40 125 C A Note 1: Logic operational for V of COM -5 V to COM +600 V. Logic state held for V of COM -5 V to COM -V . S S BS www.irf.com 2