IRS2308STRPBF Infineon

DS No.PD60266 Rev A (S)PbF IRS2308 HALF-BRIDGE DRIVER Features Packages Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V, 5 V, and 15 V input logic compatible 8-Lead PDIP 8-Lead SOIC Cross-conduction prevention logic IRS2308 IRS2308S Matched propagation delay for both channels Outputs in phase with inputs Logic and power ground +/- 5 V offset. Internal 540 ns deadtime Feature Comparison Lower di/dt gate driver for better Cross- noise immunity Input conduction Deadtime Ton/Toff Part Ground Pins logic prevention (ns) (ns) Description logic 2106 COM HIN/LIN no none 220/200 The IRS2308/IRS23084 are high volt- 21064 VSS/COM age, high speed power MOSFET and 2108 Internal 540 COM HIN/LIN yes 220/200 Programmable 540 - 5000 21084 VSS/COM IGBT drivers with dependent high and 2109 Internal 540 COM low side referenced output channels. IN/SD yes 750/200 21094 Programmable 540 - 5000 VSS/COM Proprietary HVIC and latch immune HIN/LIN yes Internal 100 160/140 2304 COM CMOS technologies enable ruggedized 2308 HIN/LIN yes Internal 540 COM 220/200 monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 V. Typical Connection up to 600 V V CC V V CC B HIN HIN HO TO LIN LIN V S LOAD COM LO (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IRS2308(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side floating absolute voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V V Low side and logic fixed supply voltage -0.3 25 CC V Low side output voltage -0.3 V + 0.3 LO CC V Logic input voltage (HIN & LIN ) V - 0.3 V + 0.3 IN SS CC dV /dt Allowable offset supply voltage transient 50 V/ns S (8 lead PDIP) 1.0 P Package power dissipation T +25 C D A W (8 lead SOIC) 0.625 (8 lead PDIP) 125 Rth Thermal resistance, junction to ambient C/W JA (8 lead SOIC) 200 T Junction temperature 150 J C T Storage temperature -50 150 S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V and V offset rating are tested with all supplies biased at a 15 V differential. S SS Symbol Definition Min. Max. Units V High side floating supply absolute voltage V + 10 V + 20 S B S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V V Low side and logic fixed supply voltage 10 20 CC V Low side output voltage 0 V LO CC V Logic input voltage COM V IN CC T Ambient temperature -40 125 C A Note 1: Logic operational for V of -5 V to +600 V. Logic state held for V of -5 V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). www.irf.com 2