CY91520 Series 32-bit FR81S Microcontroller The CY91520 series is a Cypress 32-bit microcontroller designed for automotive devices. This series contains the FR81S CPU which is compatible with the FR family. Note:This series is a composition of the end of the above-mentioned each name of articles of presence, According to Presence of sub-clock, CSV initial value and LVD initial value. Please seeOrdering Informatio for details. Features FR81S CPU Core Peripheral Functions 32-bit RISC, load/store architecture, pipeline 5-stage Clock generation (equipped with SSCG function) structure Main oscillation (4 MHz to 16 MHz) Sub oscillation (32 kHz) or none sub oscillation Maximum operating frequency: 80 MHz (Source oscillation PLL multiplication rate : 1 to 20 times = 4.0 MHz and 20 multiplied (PLL clock multiplication system)) Equipped with a 100 kHz CR oscillator General-purpose register : 32 bits 16 sets Built-in program flash memory capacity CY91F522: 256 +64 KB 16-bit fixed length instructions (basic instruction), CY91F523: 384 + 64 KB 1 instruction per cycle CY91F524: 512 + 64 KB Instructions appropriate to embedded applications CY91F525: 768 + 64 KB Memory-to-memory transfer instruction CY91F526: 1024 + 64 KB Bit processing instruction Flash memory for built-in data (WorkFlash) 64 KB Barrel shift order etc. Built-in RAM capacity High-level language support instructions Main RAM CY91F522: 48 KB Function entry/exit instructions CY91F523: 48 KB Register content multi-load and store instructions CY91F524: 64 KB CY91F525: 96 KB Bit search instructions CY91F526: 128 KB Logical 1 detection, 0 detection, and change-point detection Backup RAM 8 KB Branch instructions with delay slot General-purpose ports: Overhead reduction during branch process CY91F52xB 44 sets (No sub oscillation), 42 sets (sub Register interlock function oscillation) CY91F52xD 56 sets (No sub oscillation), 54 sets (sub Easy assembler writing oscillation) The support at the built-in / instruction level of the multiplier CY91F52xF 76 sets (No sub oscillation), 74 sets (sub oscillation) Signed 32-bit multiplication: 5 cycles CY91F52xJ 96 sets (No sub oscillation), 94 sets (sub Signed 16-bit multiplication: 3 cycles oscillation) Interrupt (PC/PS saving) CY91F52xK 120 sets (No sub oscillation), 118 sets (sub 6 cycles (16 priority levels) oscillation) CY91F52xL 152 sets (No sub oscillation), 150 sets (sub The Harvard architecture allows simultaneous execution of oscillation) program and data access. 2 Included I C open drain corresponding ports:16 sets Instruction compatibility with the FR Family External bus interface Built-in memory protection function (MPU) 22-bit address, 16-bit data Eight protection areas can be specified commonly for DMA Controller instructions and the data. Up to 16 channels can be started simultaneously. Control access privilege in both privilege mode and 2 transfer factors (Internal peripheral request and user mode. software) Built-in FPU (floating point arithmetic) A/D converter (successive approximation type) IEEE754 compliant 12-bit resolution : Max. 48 ch (32 ch + 16 ch) Floating-point register 32-bit 16 sets Conversion time : 1.4 s Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04662 Rev. *H Revised June 25, 2018 CY91520 Series 64-transmission/reception message buffering : D/A converter (R-2R type) 2 channels (ch.1 and ch.2) 8-bit resolution : 2 ch PPG: 16-bit Max. 48 channels External interrupt input: 8 channels 2 units total LED drive output 4 channels 11 ch to 14 ch 16 channels Reload timer : 16-bit Max.8 channels Level /), or edge detection (rising or falling) enabled Free-run timer : 16-bit 3 channels Multi-function serial communication (built-in 32-bit Max 3 channels transmission/reception FIFO memory) : Max.12 channels Input capture : 5 V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 16-bit 4 channels (linked to the free-run timer) CMOS hysteresis input 32-bit Max 6 channels (linked to the free-run timer) < UART (Asynchronous serial interface) > Full-duplex double buffering system, 64-step Output compare : transmission FIFO memory, 64-step reception FIFO 16-bit 6 channels (linked to the free-run timer) memory 32-bit Max 6 channels (linked to the free-run timer) Parity or no parity is selectable. Waveform generator : 6 channels Built-in dedicated baud rate generator Up/Down counter An external clock can be used as the transfer clock 8-/16-bit Up/Down counter 2 channels Parity, frame, and overrun error detection functions provided Real-time clock (RTC) (for day, hours, minutes, seconds) DMA transfer support Main or sub oscillation frequency can be selected for <CSIO (Synchronous serial interface) > the operation clock Full-duplex double buffering system, 64-step Calibration: Real-time clock (RTC) of the subclock drive transmission FIFO memory, 64-step reception FIFO memory The main clock to sub clock ratio can be corrected by setting the real-time clock prescaler SPI supported master and slave systems supported 5 to 16, 20, 24, 32-bit data length can be set. Clock Supervisor Built-in dedicated baud rate generator (Master Monitoring abnormality (by damaged quartz, etc.) of operation) suboscillation (32 kHz) (dual clock products) An external clock can be entered. (Slave operation) of the outside and main oscillation (4 MHz) Overrun error detection function is provided When abnormality is detected, it switches to the CR clock. DMA transfer support Initial value ON/OFF can be selected by the part Serial chip select SPI function number. <LIN (Asynchronous Serial Interface for LIN) > Full-duplex double buffering system, 64-step Base timer : Max.2 channels transmission FIFO memory, 64-step reception FIFO 16-bit timer memory Any of four PWM/PPG/PWC/reload timer functions can LIN protocol revision 2.1 supported be selected and used Master and slave systems supported As for the PWC function and the reload timer function, Framing error and overrun error detection a pair of 16-bit timers can be used as one 32-bit timer LIN synch break generation and detection LIN synch in the cascade mode delimiter generation CRC generation Built-in dedicated baud rate generator Watchdog timer An external clock can be adjusted by the reload Hardware watchdog counter Software watchdog (possible to set the valid range for DMA transfer support counter clearing) Hard assist function NMI (non-maskable interrupt) 2 < I C > Interrupt controller 2 channels ch.3 , ch.4 Standard mode/fast mode Interrupt request batch read supported. The interrupt existence from two or more peripherals 6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode can be read by a series of register. supported. Full-duplex double buffering system, 64-step I/O relocation transmission FIFO memory, 64-step reception FIFO Peripheral function pins can be reassigned. memory Standard mode (Max. 100 kbps) / fast mode (Max. 400 kbps) supported Low-power consumption mode DMA transfer supported (for transmission only) Sleep / Stop / Watch / Sub RUN mode Stop (power shutdown) / Watch (power shutdown) CAN Controller (CAN) : 3 channels mode Transfer speed : Up to 1 Mbps 128-transmission/reception message buffering : 1 channel (ch.0), Document Number: 002-04662 Rev. *H Page 2 of 281