Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comMB95560H Series MB95570H Series MB95580H Series New 8FX 8-bit Microcontrollers The MB95560H/570H/580H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. There are four standby modes as follows: Features Stop mode 2 F MC-8FX CPU core Sleep mode Instruction set optimized for controllers Watch mode Multiplication and division instructions Time-base timer mode 16-bit arithmetic operations In standby mode, the device can be made to enter either Bit test branch instructions normal standby mode or deep standby mode. Bit manipulation instructions, etc. I/O port MB95F562H/F563H/F564H (maximum no. of I/O ports: 16) Clock (The main oscillation clock and the suboscillation clock - General-purpose I/O ports (CMOS I/O): 15 are only available on MB95F562H/F562K/F563H/F563K/ F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.) - General-purpose I/O ports (N-ch open drain): 1 Selectable main clock source MB95F562K/F563K/F564K (maximum no. of I/O ports: 17) Main oscillation clock (up to 16.25 MHz, maximum ma- - General-purpose I/O ports (CMOS I/O): 15 chine clock frequency: 8.125 MHz) - General-purpose I/O ports (N-ch open drain): 2 External clock (up to 32.5 MHz, maximum machine clock MB95F572H/F573H/F574H (maximum no. of I/O ports: 4) frequency: 16.25 MHz) - General-purpose I/O ports (CMOS I/O): 3 Main CR clock (4 MHz 2%) - General-purpose I/O ports (N-ch open drain): 1 - The main CR clock frequency becomes 8 MHz when MB95F572K/F573K/F574K (maximum no. of I/O ports: 5) the PLL multiplication rate is 2. - General-purpose I/O ports (CMOS I/O): 3 - The main CR clock frequency becomes 10 MHz when - General-purpose I/O ports (N-ch open drain): 2 the PLL multiplication rate is 2.5. MB95F582H/F583H/F584H (maximum no. of I/O ports: 12) - The main CR clock frequency becomes 12 MHz when - General-purpose I/O ports (CMOS I/O): 11 the PLL multiplication rate is 3. - General-purpose I/O ports (N-ch open drain): 1 - The main CR clock frequency becomes 16 MHz when MB95F582K/F583K/F584K (maximum no. of I/O ports: 13) the PLL multiplication rate is 4. - General-purpose I/O ports (CMOS I/O): 11 Selectable subclock source - General-purpose I/O ports (N-ch open drain): 2 Suboscillation clock (32.768 kHz) External clock (32.768 kHz) On-chip debug Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) 1-wire serial control Serial writing supported (asynchronous mode) Timer 8/16-bit composite timer 2 channels (only one channel on Hardware/software watchdog timer MB95F572H/F572K/F573H/F573K/F574H/F574K/F582H/ Built-in hardware watchdog timer F582K/F583H/F583K/F584H/F584K) Built-in software watchdog timer Time-base timer 1 channel Watch prescaler 1 channel Power-on reset A power-on reset is generated when the power is switched LIN-UART (only available on MB95F562H/F562K/F563H/ on. F563K/F564H/F564K/F582H/F582K/F583H/F583K/F584H/ F584K) Low-voltage detection reset circuit (only available on MB95F562K/F563K/F564K/F572K/F573K/F574K/F582K/ Full duplex double buffer F583K/F584K) Capable of clock synchronous serial data transfer and clock asynchronous serial data transfer Built-in low-voltage detector External interrupt Clock supervisor counter Interrupt by edge detection (rising edge, falling edge, and Built-in clock supervisor counter function both edges can be selected) Dual operation Flash memory Can be used to wake up the device from different low power The program/erase operation and the read operation can be consumption (standby) modes executed in different banks (upper bank/lower bank) simul- 8/10-bit A/D converter taneously. 8-bit or 10-bit resolution can be selected. Flash memory security function Low power consumption (standby) modes Protects the content of the Flash memory. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04629 Rev. *E Revised November 21, 2017