MB95690K Series New 8FX 8-bit Microcontrollers The MB95690K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral functions. Waveform sequencer (including a 16-bit timer equipped with Features a buffer and a compare clear function) 2 F MC-8FX CPU core LIN-UART Instruction set optimized for controllers Full duplex double buffer Multiplication and division instructions Capable of clock asynchronous serial data transfer and clock 16-bit arithmetic operations synchronous serial data transfer Bit test branch instructions External interrupt Bit manipulation instructions, etc. FPT-44P-M25: 7 channels LQA048-02, LQC052, LCC-48P-M11: 8 channels Clock Interrupt by edge detection (rising edge, falling edge, and Selectable main clock source both edges can be selected) Main oscillation clock (up to 16.25 MHz, maximum ma- Can be used to wake up the device from different low power chine clock frequency: 8.125 MHz) consumption (standby) modes External clock (up to 32.5 MHz, maximum machine clock 8/10-bit A/D converter frequency: 16.25 MHz) FPT-44P-M25: 8 channels Main CR clock (4 MHz 2%) LQA048-02, LQC052, LCC-48P-M11: 12 channels Main CR PLL clock 8-bit or 10-bit resolution can be selected. - The main CR PLL clock frequency becomes 8 MHz 2% when the PLL multiplication rate is 2. Low power consumption (standby) modes - The main CR PLL clock frequency becomes 10 MHz There are four standby modes as follows: 2% when the PLL multiplication rate is 2.5. Stop mode - The main CR PLL clock frequency becomes 12 MHz Sleep mode 2% when the PLL multiplication rate is 3. Watch mode - The main CR PLL clock frequency becomes 16 MHz Time-base timer mode 2% when the PLL multiplication rate is 4. In standby mode, two further options can be selected: normal Selectable subclock source standby mode and deep standby mode. Suboscillation clock (32.768 kHz) I/O port External clock (32.768 kHz) FPT-44P-M25 (number of I/O ports: 41) Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) General-purpose I/O ports (CMOS I/O):37 Timer General-purpose I/O ports (N-ch open drain):4 8/16-bit composite timer 2 channels LQA048-02, LQC052, LCC-48P-M11 (number of I/O ports: 8/16-bit PPG 3 channels 45) 16-bit PPG timer 1 channel (can work independently or General-purpose I/O ports (CMOS I/O):41 together with the multi-pulse generator) General-purpose I/O ports (N-ch open drain):4 16-bit reload timer 1 channel (can work independently or On-chip debug together with the multi-pulse generator) Time-base timer 1 channel 1-wire serial control Watch prescaler 1 channel Serial writing supported (asynchronous mode) UART/SIO 1 channel Hardware/software watchdog timer Full duplex double buffer Built-in hardware watchdog timer Capable of clock asynchronous (UART) serial data transfer Built-in software watchdog timer and clock synchronous (SIO) serial data transfer Power-on reset 2 I C bus interface 1 channel A power-on reset is generated when the power is switched Built-in wake-up function on. Multi-pulse generator (MPG) (for DC motor control) 1 channel Low-voltage detection (LVD) reset circuit 16-bit reload timer 1 channel The LVD function is enabled by default. For details, see 20.2 Recommended Operating Conditions in 16-bit PPG timer 1 channel Electrical Characteristics. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04692 Rev. *B Revised September 1, 2016 MB95690K Series The LVD function can be controlled through software. Clock supervisor counter The LVD reset circuit control register (LVDCC) enables or Built-in clock supervisor counter disables the LVD reset. Dual operation Flash memory The LVD reset circuit has an internal low-voltage detector. The program/erase operation and the read operation can be The combination of detection voltage and release voltage executed in different banks (upper bank/lower bank) simul- can be selected from four options. taneously. Comparator 2 channels Flash memory security function Built-in dedicated BGR Protects the content of the Flash memory. The comparator reference voltage can be selected between the BGR voltage and the comparator pin. Document Number: 002-04692 Rev. *B Page 2 of 128