The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix CY. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world s most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB95F856K, MB95F866K, PRELIMINARY MB95F876K New 8FX MB95850K/860K/870K Series Datasheet Description The MB95850K/860K/870K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of these series contain a variety of peripheral functions. Features 2 F MC-8FX CPU core Built-in wake-up function Instruction set optimized for controllers External interrupt Multiplication and division instructions MB95F856K: 6 channels 16-bit arithmetic operations MB95F866K: 8 channels Bit test branch instructions MB95F876K: 10 channels Bit manipulation instructions, etc. Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) Clock Can be used to wake up the device from different low power Selectable main clock source consumption (standby) modes Main oscillation clock (up to 16.25 MHz, maximum ma- 8/10-bit A/D converter chine clock frequency: 8.125 MHz) MB95F856K: 4 channels External clock (up to 32.5 MHz, maximum machine clock MB95F866K: 6 channels frequency: 16.25 MHz) MB95F876K: 8 channels Main CR clock (4 MHz 2%) 8-bit or 10-bit resolution can be selected. Main CR PLL clock Low power consumption (standby) modes The main CR PLL clock frequency becomes 8 MHz 2% when the PLL multiplication rate is 2. There are four standby modes as follows: Stop mode The main CR PLL clock frequency becomes 10 MHz 2% when the PLL multiplication rate is 2.5. Sleep mode Watch mode The main CR PLL clock frequency becomes 12 MHz 2% Time-base timer mode when the PLL multiplication rate is 3. In standby mode, two further options can be selected: normal The main CR PLL clock frequency becomes 16 MHz 2% standby mode and deep standby mode. when the PLL multiplication rate is 4. Selectable subclock source I/O port Suboscillation clock (32.768 kHz) MB95F856K (number of I/O ports: 21) External clock (32.768 kHz) General-purpose I/O ports (CMOS I/O): 17 Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) General-purpose I/O ports (N-ch open drain): 4 MB95F866K (number of I/O ports: 29) Timer General-purpose I/O ports (CMOS I/O): 25 8/16-bit composite timer General-purpose I/O ports (N-ch open drain): 4 MB95F856K: 1 channel MB95F876K (number of I/O ports: 45) MB95F866K/F876K: 2 channels General-purpose I/O ports (CMOS I/O): 41 8/16-bit PPG General-purpose I/O ports (N-ch open drain): 4 MB95F856K: 1 channel MB95F866K: 2 channels On-chip debug MB95F876K: 3 channels 1-wire serial control Time-base timer 1 channel Serial writing supported (asynchronous mode) Watch counter 1 channel Hardware/software watchdog timer Watch prescaler 1 channel Built-in hardware watchdog timer UART/SIO 1 channel Built-in software watchdog timer Full duplex double buffer Power-on reset Capable of clock asynchronous (UART) serial data transfer A power-on reset is generated when the power is switched and clock synchronous (SIO) serial data transfer on. 2 I C bus interface 1 channel Low-voltage detection (LVD) reset circuit Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-09305 Rev. *C Revised January 22, 2018