MB9A110A/MB9A110 Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9A110A/MB9A110 Series are highly integrated 32-bit microcontrollers that target for high-performance and cost-sensitive embedded control applications. The MB9A110A Series are based on the ARM Cortex -M3 Processor and on-chip Flash memory and SRAM, and peripheral 2 functions, including Motor Control Timers, ADCs, Communication Interfaces (UART, CSIO, I C, LIN). The products which are described in this datasheet are placed into TYPE1 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM Cortex -M3 Core UART Processor version: r2p1 Full duplex double buffer Up to 40 MHz Frequency Operation Selection with or without parity supported Integrated Nested Vectored Interrupt Controller (NVIC): 1 Built-in dedicated baud rate generator NMI (non-maskable interrupt) and 48 peripheral interrupts External clock available as a serial clock and 16 priority levels Hardware Flow control : Automatically control the 24-bit System timer (Sys Tick): System timer for OS task transmission by CTS/RTS (only ch.4)* management Various error detection functions available (parity errors, On-chip Memories framing errors, and overrun errors) *: MB9AF111LA, F112LA, F114LA, F112L and F114L do not Flash memory support Hardware Flow control Up to 512 Kbyte CSIO Read cycle: 0 wait-cycle Full duplex double buffer Security function for code protection Built-in dedicated baud rate generator SRAM Overrun error detection function available This Series contain a total of up to 32 Kbyte on-chip SRAM. LIN On-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and LIN protocol Rev.2.1 supported D-code bus of Cortex-M3 core. SRAM1 is connected to System Full duplex double buffer bus. Master/Slave mode supported SRAM0: Up to 16 Kbytes LIN break field generation (can be changed 13- 16bit length) SRAM1: Up to 16 Kbytes LIN break delimiter generation (can be changed 1 - 4bit Multi-function Serial Interface (Max 8 channels) length) 4 channels with 16 steps9bit FIFO (ch.4-ch.7), 4 channels Various error detection functions available (parity errors, without FIFO (ch.0-ch3) framing errors, and overrun errors) 2 Operation mode is selectable from the followings for each I C channel. Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) UART supported CSIO LIN 2 I C Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04672 Rev. *E Revised June 24, 2019 MB9A110A/MB9A110 Series External Bus Interface* Multi-function Timer (Max 2 units) The Multi-function timer is composed of the following blocks. Supports SRAM, NOR Flash device 16-bit free-run timer 3 ch/unit Up to 8 chip selects Input capture 4 ch/unit 8-/16-bit Data width Output compare 6 ch/unit Up to 25-bit Address bit A/D activation compare 3 ch/unit Maximum area size: Up to 256 Mbytes Waveform generator 3 ch/unit Supports Address/Data multiplex 16-bit PPG timer 3 ch/unit Supports external RDY function *: MB9AF111LA, F112LA and F114LA do not support The following function can be used to achieve the motor External Bus Interface control. DMA Controller (8 channels) PWM signal output function The DMA Controller has an independent bus from the CPU, so DC chopper waveform output function CPU and DMA Controller can process simultaneously. Dead timer function 8 independently configured and operated channels Input capture function Transfer can be started by software or request from the built-in peripherals A/D converter activate function Transfer address area: 32bit (4 Gbytes) DTIF (Motor emergency stop) interrupt function Transfer mode: Block transfer/Burst transfer/Demand Quadrature Position/Revolution Counter (QPRC) transfer (Max 2 units) Transfer data type: byte/half-word/word The Quadrature Position/Revolution Counter (QPRC) is used Transfer block count: 1 to 16 to measure the position of the position encoder. Moreover, it is possible to use up/down counter. Number of transfers: 1 to 65536 The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. A/D Converter (Max 16 channels) 16-bit position counter 12-bit A/D Converter 16-bit revolution counter Successive Approximation type Two 16-bit compare registers Built-in 3units* Conversion time: 1.0 s 5 V Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down Priority conversion available (priority at 2levels) counters. Scanning conversion mode Operation mode is selectable from the followings for each timer channel. Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4steps) Free-running *: MB9AF111LA, F112LA, F114LA built-in 2units Periodic (=Reload) Base Timer (Max 8 channels) One-shot Operation mode is selectable from the followings for each channel. Watch Counter 16-bit PWM timer The Watch counter is used for wake up from Low-Power Consumption mode. 16-bit PPG timer Interval timer: up to 64 s(Max) Sub Clock: 32.768 kHz 16-/32-bit reload timer 16-/32-bit PWC timer Document Number: 002-04672 Rev. *E Page 2 of 111