The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix CY. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world s most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB9B110R Series 32-bit Arm Cortex -M3 FM3 Microcontroller The MB9B110R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and has 2 peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE4 product categories in FM3 Family Peripheral Manual. Features External Bus Interface Supports SRAM, NOR and NAND Flash device 32-bit Arm Cortex-M3 Core Up to 8 chip selects Processor version: r2p1 8-/16-bit Data width Up to 25-bit Address bit Up to 144 MHz Frequency Operation Maximum area size: Up to 256 Mbytes Memory Protection Unit (MPU): improves the reliability of an embedded system Supports Address/Data multiplex Supports external RDY input Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels Multi-function Serial Interface (Max eight channels) 24-bit System timer (Sys Tick): System timer for OS task 4 channels with 16 steps9-bit FIFO (ch.4-ch.7), 4 channels management without FIFO (ch.0-ch.3) Operation mode is selectable from the followings for each channel. On-chip Memories UART Flash memory CSIO LIN These series are based on two independent on-chip Flash 2 I C memories. UART MainFlash Full-duplex double buffer Up to 512 Kbyte Selection with or without parity supported Built-in Flash Accelerator System with 16 Kbyte trace buffer Built-in dedicated baud rate generator memory External clock available as a serial clock The read access to Flash memory can be achieved without Hardware Flow control: Automatically control the wait cycle up to operation frequency of 72 MHz. Even at the transmission by CTS/RTS (only ch.4) operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Various error detect functions available (parity errors, Accelerator System. framing errors, and overrun errors) Security function for code protection CSIO Full-duplex double buffer WorkFlash 32 Kbyte Built-in dedicated baud rate generator Read cycle Overrun error detect function available 4 wait-cycle: the operation frequency more than 72 MHz LIN 2 wait-cycle: the operation frequency more than 40 MHz, and LIN protocol Rev.2.1 supported to 72 MHz Full-duplex double buffer 0wait-cycle: the operation frequency to 40 MHz Master/Slave mode supported Security function is shared with code protection LIN break field generate (can be changed 13 to 16-bit length) SRAM LIN break delimiter generate (can be changed 1 to 4-bit This Series contain a total of up to 64 Kbyte on-chip SRAM. length) This is composed of two independent SRAM (SRAM0, Various error detect functions available (parity errors, framing errors, and overrun errors) SRAM1). SRAM0 is connected to I-code bus and D-code bus 2 I C of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 32 Kbyte Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported SRAM1: Up to 32 Kbyte Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05622 Rev. *D Revised February 9, 2018