MB9BF116S/T MB9BF117S/T MB9BF118S/T FM3, MB9B110T Series, 32-bit ARM Cortex -M3 based Microcontroller Datasheet The MB9B110T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have 2 peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE2 product categories in FM3 Family PERIPHERAL MANUA. Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. Features 32-bit ARM Cortex-M3 Core External Bus Interface Processor version: r2p1 Supports SRAM, NOR and NAND Flash memory devices Up to 144 MHz Frequency Operation Up to 8 chips selected Memory Protection Unit (MPU):improves the reliability of an embedded system 8-/16-bit Data width Integrated Nested Vectored Interrupt Controller Up to 25-bit Address bit (NVIC): 1 NMI (non-maskable interrupt) and 48 Maximum area size: Up to 256 Mbytes peripheral interrupts and 16 priority levels Supports Address/Data multiplex 24-bit System timer (Sys Tick): System timer for OS Supports external RDY function task management Multi-function Serial Interface (Max 8 channels) On-chip Memories 4 channels with 16steps9-bit FIFO (ch.4 to ch.7), 4 Flash memory channels without FIFO (ch.0 to ch.3) Up to 1 Mbyte Operation mode is selectable from the followings for Built-in Flash memory Accelerator System with 16 each channel. Kbyte trace buffer memory UART The read access to Flash memory can be achieved CSIO without wait cycle up to the operation frequency of LIN 72MHz. Even at the operation frequency more than I2C 72 MHz, an equivalent access to Flash memory can be obtained by Flash memory Accelerator System. UART Security function for code protection Full-duplex double buffer SRAM Selection with or without parity supported This Series on-chip SRAM is composed of two Built-in dedicated baud rate generator independent SRAMs (SRAM0,SRAM1) . SRAM0 is External clock available as a serial clock connected to I-code bus and D-code bus of Cortex-M3 Hardware Flow control: Automatically controls the core. SRAM1 is connected to System bus. transmission/reception with CTS/RTS (only for ch.4) SRAM0: Up to 64 Kbytes. Various error detection functions available (parity SRAM1: Up to 64 Kbytes. errors, framing errors, and overrun errors) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04683 Rev.*A Revised April 7, 2016 MB9B110T Series Base Timer (Max 16 channels) CSIO Operation mode is selectable from the followings for Full-duplex double buffer each channel. Built-in dedicated baud rate generator 16-bit PWM timer Overrun error detection function available 16-bit PPG timer LIN 16-/32-bit reload timer LIN protocol Rev.2.1 supported 16-/32-bit PWC timer Full-duplex double buffer Master/Slave mode supported General-Purpose I/O Port LIN break field generation (can be changed to 13-bit This series can use its pins as I/O ports when they are length to 16-bit) not used for an external bus or peripherals. Moreover, LIN break delimiter generation (can be changed to the port relocate function is built in. It can set which I/O 1-bit length to 4-bit) port the peripheral function can be allocated to. Various error detection functions available (parity Capable of pull-up control per pin errors, framing errors, and overrun errors) 2 Capable of reading pin level directly I C Standard-mode (Max 100 kbps) / Fast-mode (Max 400 Built-in port relocate function kbps) supported Up to 154 fast I/O Ports 176 pin Package Some ports are 5 V tolerant I/O. DMA Controller (8 channels) SeePin Assignmen to confirm the corresponding The DMA Controller has a dedicated bus independent pins. from the CPU, so CPU and DMA Controller can process Multi-function Timer (Max 3 units) simultaneously. 8 independently configured and operated channels The Multi-function timer is composed of the following blocks. Transfer can be started by software or request from the built-in peripherals 16-bit free-run timer 3ch./unit Transfer address area: 32 bits (4 Gbytes) Input capture 4ch./unit Transfer mode: Block transfer/Burst transfer/Demand Output compare 6ch./unit transfer A/D activation compare 3ch./unit Transfer data type: byte/half-word/word Waveform generator 3ch./unit Transfer block count: 1 to 16 16-bit PPG timer 3ch./unit Number of transfers: 1 to 65536 The following function can be used to achieve the motor A/D Converter (Max 32 channels) control. 12-bit A/D Converter PWM signal output function Successive Approximation type DC chopper waveform output function Built-in 3units Dead time function Conversion time: 1.0s 5V Input capture function Priority conversion available (priority at 2 levels) A/D convertor activate function Scanning conversion mode DTIF (Motor emergency stop) interrupt function Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) Document Number: 002-04683 Rev.*A Page 2 of 132