The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix CY. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world s most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB9B120J Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9B120J Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions 2 such as various timers, ADCs and Communication Interfaces (UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE10 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM Cortex -M3 Core CSIO Processor version: r2p1 Full-duplex double buffer Up to 72 MHz Frequency Operation Built-in dedicated baud rate generator Integrated Nested Vectored Interrupt Controller (NVIC): 1 Overrun error detection function available NMI (non-maskable interrupt) and 48 peripheral interrupts LIN and 16 priority levels LIN protocol Rev.2.1 supported 24-bit System timer (Sys Tick): System timer for OS task management Full-duplex double buffer Master/Slave mode supported On-chip Memories LIN break field generate (can be changed 13-bit to 16-bit Flash memory length) 64 Kbytes LIN break delimiter generate (can be changed 1-bit to 4-bit length) Read cycle: 0 wait-cycle Various error detect functions available (parity errors, framing Security function for code protection errors, and overrun errors) SRAM 2 I C This Series on-chip SRAM is composed of two independent Standard-mode (Max 100 kbps) / Fast-mode (Max 400kbps) SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus supported and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. DMA Controller (Four channels) SRAM0: 4 Kbytes The DMA Controller has an independent bus from the CPU, so SRAM1: 4 Kbytes CPU and DMA Controller can process simultaneously. 4 independently configured and operated channels Multi-function Serial Interface (Max four channels) Transfer can be started by software or request from the 2 channels with 16steps9-bit FIFO (ch.0/ch.1), 2 channels built-in peripherals without FIFO (ch.2/ ch.5) Transfer address area: 32-bit (4 Gbytes) Operation mode is selectable from the followings for each Transfer mode: Block transfer/Burst transfer/Demand channel. transfer UART CSIO Transfer data type: byte/half-word/word LIN 2 Transfer block count: 1 to 16 I C Number of transfers: 1 to 65536 UART Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions available (parity errors, framing errors, and overrun errors) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05657 Rev.*C Revised June 20, 2017