MB9B300B Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9B300B Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. The MB9B300B Series are based on the ARM Cortex -M3 Processor and on-chip Flash memory and SRAM, and peripheral 2 functions, including Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I C, LIN). The products which are described in this datasheet are placed into TYPE0 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM Cortex -M3 Core USB host Processor version: r2p0 USB2.0 Full/Low-speed supported Up to 80 MHz Frequency Operation Bulk-transfer and interrupt-transfer and Isochronous-transfer support Memory Protection Unit (MPU): improve the reliability of an embedded system USB Device connected/dis-connected automatically detect Integrated Nested Vectored Interrupt Controller (NVIC): 1 IN/OUT token handshake packet automatically NMI (non-maskable interrupt) and 48 peripheral interrupts Max 256-byte packet-length supported and 16 priority levels Wake-up function supported 24-bit System timer (Sys Tick): System timer for OS task management Multi-function Serial Interface (Max. 8 channels) On-chip Memories 4 channels with 16steps 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3) Flash memory Operation mode is selectable from the followings for each Up to 512 KB channel. 1 Read cycle: 0 wait-cycle up to 60 MHz, 2 wait-cycle UART above CSIO 1 : Instruction pre-fetch buffer is included. So when CPU LIN 2 access continuously, it becomes 0 wait-cycle I C Security function for code protection UART SRAM Full-duplex double buffer This series contain a total of up to 64 KB on-chip SRAM. This is Selection with or without parity supported composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Built-in dedicated baud rate generator Cortex-M3 core. SRAM1 is connected to System bus. External clock available as a serial clock SRAM0: Up to 32 KB Hardware Flow control: Automatically control the SRAM1: Up to 32 KB transmission by CTS/RTS (only ch.4) Various error detect functions available (parity errors, framing USB Interface errors, and overrun errors) The USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by CSIO multiplication of Main clock. Full-duplex double buffer USB Device Built-in dedicated baud rate generator USB2.0 Full-Speed supported Overrun error detect function available Max 6 EndPoint supported EndPoint 0 is control transfer EndPoint 1 - 5 can be selected bulk-transfer or interrupt-transfer Endpoint1-5 is comprised Double Buffers. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05612 Rev. *C Revised July 13, 2017 MB9B300B Series LIN Base Timer (Max. 8 channels) Operation mode is selectable from the followings for each LIN protocol Rev.2.1 supported channel. Full duplex double buffer 16-bit PWM timer Master/Slave mode supported 16-bit PPG timer LIN break field generate (can be changed 13-16 bit length) 16-/32-bit reload timer LIN break delimiter generate (can be changed 1- 4 bit length) 16-/32-bit PWC timer Various error detect functions available (parity errors, framing errors, and overrun errors) Multi-function Timer (Max. 2 units) 2 The Multi-function timer is composed of the following blocks. I C Standard-mode (Max.100 kbps) / Fast-mode (Max 400 kbps) 16-bit free-run timer 3ch/unit supported Input capture 4ch/unit External Bus Interface Output compare 6ch/unit A/D activation compare 3ch/unit Supports SRAM, NOR& NAND Flash device Waveform generator 3ch/unit Up to 8 chip selects 16-bit PPG timer 3ch/unit 8-/16-bit Data width Up to 25-bit Address bit The following function can be used to achieve the motor Maximum area size: Up to 256 MB control. PWM signal output function DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and DC chopper waveform output function DMA Controller can process simultaneously. Dead time function 8 independently configured and operated channels Input capture function Transfer can be started by software or request from the A/D convertor activate function built-in peripherals DTIF (Motor emergency stop) interrupt function Transfer address area: 32 bit (4GB) Transfer mode: Block transfer/Burst transfer/Demand Quadrature Position/Revolution Counter (QPRC) transfer (Max. 2 units) Transfer data type: byte/half-word/word The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is Transfer block count: 1 to 16 possible to use up/down counter. Number of transfers: 1 to 65536 The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. A/D Converter (Max. 16 channels) 16-bit position counter 12-bit A/D Converter 16-bit revolution counter Successive Approximation Register type Two 16-bit compare registers Built-in 3unit Dual Timer (Two 32/16-bit Down Counter) Conversion time: 1.0 s 5 V The Dual Timer consists of two programmable 32/16-bit down Priority conversion available (priority at 2 levels) counters. Operation mode is selectable from the followings for each Scanning conversion mode channel. Built-in FIFO for conversion data storage (for SCAN Free-running conversion: 16 steps, for Priority conversion: 4steps) Periodic (=Reload) One-shot Document Number: 002-05612 Rev. *C Page 2 of 110