MB9B310T Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9B310T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions 2 such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE2 product categories inFM3 Family Peripheral Manua. Features 32-bit ARM Cortex -M3 Core External Bus Interface Processor version: r2p1 Supports SRAM, NOR and NAND Flash device Up to 144 MHz Frequency Operation Up to 8 chip selects Memory Protection Unit (MPU):improves the reliability of an 8-/16-bit Data width embedded system Up to 25-bit Address bit Integrated Nested Vectored Interrupt Controller (NVIC): 1 Maximum area size: Up to 256 Mbytes NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels Supports Address/Data multiplex 24-bit System timer (Sys Tick): System timer for OS task Supports external RDY input management USB Interface (Max 2 channels) On-chip Memories USB interface is composed of Function and Host. Flash memory USB function Up to 1 Mbyte USB2.0 Full-Speed supported Built-in Flash Accelerator System with 16 Kbyte trace buffer Max 6 EndPoint supported memory EndPoint 0 is control transfer The read access to Flash memory can be achieved without EndPoint 1, 2 can be selected Bulk-transfer, wait cycle up to operation frequency of 72MHz. Even at the Interrupt-transfer or Isochronous-transfer operation frequency more than 72MHz, an equivalent access EndPoint 3 to 5 can be selected Bulk-transfer or to Flash memory can be obtained by Flash Accelerator Interrupt-transfer System. EndPoint 1 to 5 is comprised Double Buffer EndPoint 0, 2 to 5:64 bytes Security function for code protection EndPoint 1: 256 bytes SRAM USB host This Series contain a total of up to 128Kbyte on-chip SRAM memories. This is composed of two independent SRAM USB2.0 Full/Low speed supported (SRAM0, SRAM1). SRAM0 is connected to I-code bus and Bulk-transfer, interrupt-transfer and Isochronous-transfer D-code bus of Cortex-M3 core. SRAM1 is connected to System support bus. USB Device connected/dis-connected automatically detect SRAM0: Up to 64 Kbyte. IN/OUT token handshake packet automatically SRAM1: Up to 64 Kbyte. Max 256-byte packet-length supported Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04686 Rev.*A Revised March 31, 2016 MB9B310T Series Multi-function Serial Interface (Max 8 channels) DMA Controller (8channels) DMA Controller has an independent bus for CPU, so CPU and 4 channels with 16steps9-bit FIFO (ch.4 to ch.7), 4 DMA Controller can process simultaneously. channels without FIFO (ch.0 to ch.3) 8 independently configured and operated channels Operation mode is selectable from the followings for each channel. Transfer can be started by software or request from the built-in peripherals UART CSIO Transfer address area: 32-bit (4 Gbyte) LIN 2 Transfer mode: Block transfer/Burst transfer/Demand I C transfer UART Transfer data type: byte/half-word/word Full-duplex double buffer Transfer block count: 1 to 16 Selection with or without parity supported Number of transfers: 1 to 65536 Built-in dedicated baud rate generator A/D Converter (Max 32 channels) External clock available as a serial clock 12-bit A/D Converter Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) Successive Approximation Register type Various error detect functions available (parity errors, framing Built-in 3units errors, and overrun errors) Conversion time: 1.0 s 5 V CSIO Priority conversion available (priority at 2 levels) Full-duplex double buffer Scanning conversion mode Built-in dedicated baud rate generator Built-in FIFO for conversion data storage (for SCAN Overrun error detect function available conversion: 16 steps, for Priority conversion: 4 steps) LIN LIN protocol Rev.2.1 supported Base Timer (Max 16 channels) Operation mode is selectable from the followings for each Full-duplex double buffer channel. Master/Slave mode supported 16-bit PWM timer LIN break field generate (can be changed 13 to 16-bit length) 16-bit PPG timer LIN break delimiter generate (can be changed 1 to 4-bit 16-/32-bit reload timer length) 16-/32-bit PWC timer Various error detect functions available (parity errors, framing errors, and overrun errors) General Purpose I/O Port 2 I C This series can use its pins as I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) function is built in. It can set which I/O port the peripheral supported function can be allocated. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up 154 fast I/O Ports 176 pin Package Some pin is 5V tolerant I/O. SeePin Descriptio to confirm the corresponding pins. Document Number: 002-04686 Rev.*A Page 2 of 128