MB9B400A Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9B400A Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. The MB9B400A Series are based on the ARM Cortex -M3 Processor and on-chip Flash memory and SRAM, and peripheral 2 functions, including Motor Control Timers, ADCs and Communication Interfaces (CAN, UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE0 product categories inFM3 Family Peripheral Manua. Features 32-bit ARM Cortex -M3 Core Multi-function Serial Interface (Max. 8 channels) Processor version: r2p0 4 channels with 16steps 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3) Up to 80MHz Frequency Operation Operation mode is selectable from the followings for each Memory Protection Unit (MPU): improve the reliability of an channel. embedded system UART Integrated Nested Vectored Interrupt Controller (NVIC): 1 CSIO NMI (non-maskable interrupt) and 48 peripheral interrupts LIN 2 and 16 priority levels I C 24-bit System timer (Sys Tick): System timer for OS task UART management Full-duplex double buffer On-chip Memories Selection with or without parity supported Flash memory Built-in dedicated baud rate generator Up to 512 Kbyte External clock available as a serial clock Read cycle: 0wait-cycle up to 60MHz, 2wait-cycle* above Hardware Flow control : Automatically control the *: Instruction pre-fetch buffer is included. So when CPU transmission by CTS/RTS (only ch.4) access continuously, it becomes 0wait-cycle Various error detect functions available (parity errors, framing Security function for code protection errors, and overrun errors) SRAM CSIO This series contain a total of up to 64Kbyte on-chip SRAM. This Full-duplex double buffer is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Built-in dedicated baud rate generator Cortex-M3 core. SRAM1 is connected to System bus. Overrun error detect function available SRAM0: Up to 32 Kbyte LIN SRAM1: Up to 32 Kbyte LIN protocol Rev.2.1 supported CAN Interface (Max. 2 channels) Full-duplex double buffer Compatible with CAN Specification 2.0A/B Master/Slave mode supported Maximum transfer rate: 1 Mbps LIN break field generate (can be changed 13-16bit length) Built-in 32 message buffer LIN break delimiter generate (can be changed 1-4bit length) Various error detect functions available (parity errors, framing errors, and overrun errors) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05610 Rev.*B Revised June 28, 2016 MB9B400A Series 2 I C Multi-function Timer (Max. 2 units) The Multi-function timer is composed of the following blocks. Standard-mode (Max.100kbps) / Fast-mode (Max.400Kbps) supported 16-bit free-run timer 3ch/unit Input capture 4ch/unit External Bus Interface Output compare 6ch/unit Supports SRAM, NOR& NAND Flash device A/D activation compare 3ch/unit Up to 8 chip selects Waveform generator 3ch/unit 8/16-bit Data width 16-bit PPG timer 3ch/unit Up to 25-bit Address bit The following function can be used to achieve the motor Maximum area size : Up to 256 Mbytes control. DMA Controller (8 channels) PWM signal output function DMA Controller has an independent bus for CPU, so CPU and DC chopper waveform output function DMA Controller can process simultaneously. Dead time function 8 independently configured and operated channels Input capture function Transfer can be started by software or request from the built-in peripherals A/D convertor activate function Transfer address area: 32bit(4Gbyte) DTIF (Motor emergency stop) interrupt function Transfer mode: Block transfer/Burst transfer/Demand transfer Quadrature Position/Revolution Counter (QPRC) (Max. 2 units) Transfer data type: byte/half-word/word The Quadrature Position/Revolution Counter (QPRC) is used Transfer block count: 1 to 16 to measure the position of the position encoder. Moreover, it is possible to use up/down counter. Number of transfers: 1 to 65536 The detection edge of the three external event input pins AIN, A/D Converter (Max. 16 channels) BIN and ZIN is configurable. 16-bit position counter 12-bit A/D Converter 16-bit revolution counter Successive Approximation Register type Two 16-bit compare registers Built-in 3unit Dual Timer (Two 32-/16-bit Down Counter) Conversion time: 1.0s 5V The Dual Timer consists of two programmable 32/16-bit down Priority conversion available (priority at 2levels) counters. Operation mode is selectable from the followings for each Scanning conversion mode channel. Built-in FIFO for conversion data storage (for SCAN Free-running conversion: 16steps, for Priority conversion: 4steps) Periodic (=Reload) Base Timer (Max. 8 channels) One-shot Operation mode is selectable from the followings for each channel. Watch Counter 16-bit PWM timer The Watch counter is used for wake up from sleep mode. 16-bit PPG timer Interval timer: up to 64s (Max.) Sub Clock : 32.768 kHz 16/32-bit reload timer 16/32-bit PWC timer Document Number: 002-05610 Rev.*B Page 2 of 105