MB9BF416S/T MB9BF417S/T MB9BF418S/T 32-bit ARM Cortex-M3 based Microcontroller Datasheet The MB9B410T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (CAN, UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE2 product categories inFM3 Family PERIPHERAL MANUA. Features Up to 25-bit Address bit 32-bit ARM Cortex-M3 Core Maximum area size : Up to 256 Mbytes Processor version: r2p1 Supports Address/Data multiplex Up to 144 MHz Frequency Operation Supports external RDY input Memory Protection Unit (MPU):improves the reliability of an embedded system CAN Interface (Max. 2channels) Integrated Nested Vectored Interrupt Controller (NVIC): 1 Compatible with CAN Specification 2.0A/B NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels Maximum transfer rate: 1 Mbps 24-bit System timer (Sys Tick): System timer for OS task Built-in 32 message buffer management Multi-function Serial Interface (Max 8channels) On-chip Memories 4 channels with 16steps9-bit FIFO (ch.4 to ch.7), 4 Flash memory channels without FIFO (ch.0 to ch.3) Up to 1 Mbyte Operation mode is selectable from the followings for each Built-in Flash Accelerator System with 16Kbyte trace buffer channel. memory UART CSIO The read access to Flash memory can be achieved without LIN wait cycle up to operation frequency of 72MHz. Even at the 2 operation frequency more than 72MHz, an equivalent access I C to Flash memory can be obtained by Flash Accelerator System. UART Security function for code protection Full-duplex double buffer Selection with or without parity supported SRAM This Series contain a total of up to 128 Kbyte on-chip SRAM Built-in dedicated baud rate generator memories. This is composed of two independent SRAM External clock available as a serial clock (SRAM0,SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System Hardware Flow control : Automatically control the bus. transmission by CTS/RTS (only ch.4) SRAM0: Up to 64 Kbyte. Various error detect functions available (parity errors, framing errors, and overrun errors) SRAM1: Up to 64 Kbyte. CSIO External Bus Interface Full-duplex double buffer Supports SRAM, NOR and NAND Flash device Built-in dedicated baud rate generator Up to 8 chip selects Overrun error detect function available 8-/16-bit Data width Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04689 Rev.*A Revised March 10, 2016 MB9B410T Series LIN function is built in. It can set which I/O port the peripheral function can be allocated. LIN protocol Rev.2.1 supported Capable of pull-up control per pin Full-duplex double buffer Capable of reading pin level directly Master/Slave mode supported Built-in the port relocate function LIN break field generate (can be changed 13-16-bit length) Up 154 fast I/O Ports 176pin Package LIN break delimiter generate (can be changed 1-4-bit length) Some pin is 5V tolerant I/O. Various error detect functions available (parity errors, framing See Pin Descriptio to confirm the corresponding pins. errors, and overrun errors) Multi-function Timer (Max 3 units) 2 I C The Multi-function timer is composed of the following blocks. Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) 16-bit free-run timer 3ch/unit supported Input capture 4ch/unit DMA Controller (8 channels) Output compare 6ch/unit DMA Controller has an independent bus for CPU, so CPU and A/D activation compare 3ch/unit DMA Controller can process simultaneously. Waveform generator 3ch/unit 8 independently configured and operated channels 16-bit PPG timer 3ch/unit Transfer can be started by software or request from the built-in peripherals The following function can be used to achieve the motor Transfer address area: 32 bit (4 Gbyte) control. Transfer mode: Block transfer/Burst transfer/Demand PWM signal output function transfer DC chopper waveform output function Transfer data type: byte/half-word/word Dead time function Transfer block count: 1 to 16 Input capture function Number of transfers: 1 to 65536 A/D convertor activate function A/D Converter (Max 32 channels) DTIF (Motor emergency stop) interrupt function 12-bit A/D Converter Successive Approximation Register type Quadrature Position/Revolution Counter (QPRC) Built-in 3unit (Max 3 channels) The Quadrature Position/Revolution Counter (QPRC) is used Conversion time: 1.0 s 5 V to measure the position of the position encoder. Moreover, it is possible to use up/down counter. Priority conversion available (priority at 2 levels) Scanning conversion mode The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4steps) 16-bit position counter 16-bit revolution counter Base Timer (Max 16 channels) Two 16-bit compare registers Operation mode is selectable from the followings for each channel. Dual Timer (32-/16bit Down Counter) 16-bit PWM timer The Dual Timer consists of two programmable 32-/16-bit down 16-bit PPG timer counters. Operation mode is selectable from the followings for each 16-/32-bit reload timer channel. 16-/32-bit PWC timer Free-running Periodic (=Reload) General Purpose I/O Port This series can use its pins as I/O ports when they are not used One-shot for external bus or peripherals. Moreover, the port relocate Document Number: 002-04689 Rev.*A Page 2 of 122