MB9B500B Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9B500B Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. The MB9B500B Series are based on the ARM Cortex -M3 Processor and on-chip Flash memory and SRAM, and peripheral 2 functions, including Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE0 product categories inFM3 Family Peripheral Manua. Features USB Device 32-bit ARM Cortex -M3 Core USB2.0 Full-Speed supported Processor version: r2p0 Max. 6 EndPoint supported Up to 80 MHz Frequency Operation EndPoint 0 is control transfer Memory Protection Unit (MPU): improve the reliability of an EndPoint 1-5 can be selected bulk-transfer or embedded system interrupt-transfer Integrated Nested Vectored Interrupt Controller (NVIC): 1 EndPoint 1-5 is comprised Double Buffer NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels USB Host 24-bit System timer (Sys Tick): System timer for OS task USB2.0 Full/Low speed supported management Bulk-transfer and interrupt-transfer and Isochronous-transfer support On-chip Memories USB Device connected/dis-connected automatically detect Flash memory IN/OUT token handshake packet automatically Up to 512 Kbyte Max.256-byte packet-length supported Read cycle: 0wait-cycle up to 60 MHz, 2wait-cycle* above Wake-up function supported *: Instruction pre-fetch buffer is included. So when CPU access continuously, it becomes 0wait-cycle CAN Interface (Max. 2 channels) Security function for code protection Compatible with CAN Specification 2.0A/B SRAM Maximum transfer rate: 1 Mbps This series contain a total of up to 64 Kbyte on-chip SRAM. Built-in 32 message buffer This is composed of two independent SRAM(SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Multi-function Serial Interface (Max. 8 channels) Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 32 Kbyte 4 channels with 16steps 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3) SRAM1: Up to 32 Kbyte Operation mode is selectable from the followings for each channel. USB Interface UART USB interface is composed of Device and Host. CSIO PLL for USB is built-in, USB clock can be generated by LIN multiplication of Main clock. 2 I C Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05607 Rev.*D Revised July 13, 2017 MB9B500B Series UART DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and Full-duplex double buffer DMA Controller can process simultaneously. Selection with or without parity supported 8 independently configured and operated channels Built-in dedicated baud rate generator Transfer can be started by software or request from the built-in peripherals External clock available as a serial clock Transfer address area: 32 bit(4 Gbyte) Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4) Transfer mode: Block transfer/Burst transfer/Demand transfer Various error detect functions available (parity errors, framing errors, and overrun errors) Transfer data type: byte/half-word/word Transfer block count: 1 to 16 CSIO Number of transfers: 1 to 65536 Full-duplex double buffer Built-in dedicated baud rate generator A/D Converter (Max. 16 channels) Overrun error detect function available 12-bit A/D Converter LIN Successive Approximation Register type LIN protocol Rev.2.1 supported Built-in 3unit Full-duplex double buffer Conversion time: 1.0 s 5 V Master/Slave mode supported Priority conversion available (priority at 2levels) LIN break field generate (can be changed 13-16bit length) Scanning conversion mode LIN break delimiter generate (can be changed 1-4bit length) Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) Various error detect functions available (parity errors, framing errors, and overrun errors) Base Timer (Max. 8 channels) 2 I C Operation mode is selectable from the followings for each channel. Standard-mode (Max.100 kbps) / Fast-mode (Max.400 kbps) 16-bit PWM timer supported 16-bit PPG timer External Bus Interface 16-/32-bit reload timer Supports SRAM, NOR& NAND Flash device 16-/32-bit PWC timer Up to 8 chip selects Multi-function Timer (Max. 2 units) 8-/16-bit Data width The Multi-function timer is composed of the following blocks. Up to 25-bit Address bit 16-bit free-run timer 3 ch/unit Maximum area size: Up to 256 Mbytes Input capture 4 ch/unit Output compare 6 ch/unit A/D activation compare 3 ch/unit Waveform generator 3 ch/unit 16-bit PPG timer 3 ch/unit Document Number: 002-05607 Rev.*D Page 2 of 114