The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix CY. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world s most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB9B510R Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9B510R Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has 2 peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE4 product categories in FM3 Family Peripheral Manual. Features External Bus Interface 32-bit ARM Cortex-M3 Core Supports SRAM, NOR and NAND Flash device Processor version: r2p1 Up to 8 chip selects Up to 144 MHz Frequency Operation 8-/16-bit Data width Memory Protection Unit (MPU): improves the reliability of an Up to 25-bit Address bit embedded system Integrated Nested Vectored Interrupt Controller (NVIC): 1 Maximum area size: Up to 256 Mbytes NMI (non-maskable interrupt) and 48 peripheral interrupts Supports Address/Data multiplex and 16 priority levels Supports external RDY input 24-bit System timer (Sys Tick): System timer for OS task management USB Interface On-chip Memories USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by Flash memory multiplication of Main clock. These series are based on two independent on-chip Flash USB device memories. USB2.0 Full-Speed supported MainFlash Max 6 EndPoint supported Up to 512 Kbyte EndPoint 0 is control transfer Built-in Flash Accelerator System with 16 Kbyte trace EndPoint 1, 2 can be selected Bulk-transfer, buffer memory Interrupt-transfer or Isochronous-transfer The read access to Flash memory can be achieved without EndPoint 3 to 5 can be selected Bulk-transfer or wait cycle up to operation frequency of 72 MHz. Even at Interrupt-transfer the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash EndPoint 1 to 5 is comprised Double Buffer Accelerator System. The size of each EndPoint is as follows. Security function for code protection EndPoint 0, 2 to 5: 64 bytes WorkFlash EndPoint 1: 256 bytes 32 Kbyte USB host Read cycle USB2.0 Full/Low-speed supported 4wait-cycle: the operation frequency more than 72 MHz Bulk-transfer, interrupt-transfer and Isochronous-transfer 2wait-cycle: the operation frequency more than 40 MHz, support and to 72 MHz USB Device connected/dis-connected automatically detect 0wait-cycle: the operation frequency to 40 MHz IN/OUT token handshake packet automatically Security function is shared with code protection Max 256-byte packet-length supported Wake-up function supported SRAM This Series contain a total of up to 64 Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, CAN Interface (Max two channels) SRAM1). SRAM0 is connected to I-code bus and D-code bus Compatible with CAN Specification 2.0A/B of Cortex-M3 core. SRAM1 is connected to System bus. Maximum transfer rate: 1 Mbps SRAM0: Up to 32 Kbyte Built-in 32 message buffer SRAM1: Up to 32 Kbyte Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-08541 Rev.*C Revised March 21, 2017