The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix CY. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world s most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB9B560R Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the MB9B560R Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex -M4F Processor with on-chip Flash memory and SRAM. The series has peripheral 2 functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN). Features 32-bit ARM Cortex -M4F Core SRAM This is composed of three independent SRAMs (SRAM0, Processor version: r0p1 SRAM1, and SRAM2). SRAM0 is connected to I-code bus and Up to 160 MHz Frequency Operation D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. FPU built-in SRAM0: Up to 64 Kbytes Support DSP instruction SRAM1: Up to 32 Kbytes Memory Protection Unit (MPU): improves the reliability of an embedded system SRAM2: Up to 32 Kbytes Integrated Nested Vectored Interrupt Controller (NVIC): 1 External Bus Interface NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels Supports SRAM, NOR, NAND Flash, and SDRAM device 24-bit System timer (Sys Tick): System timer for OS task Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) management 8-/16-bit Data width Up to 25-bit Address bit On-chip Memories Maximum Access size: 256M byte Flash memory Supports Address/Data multiplex These series are based on two independent on-chip Flash Supports external RDY function memories. Supports scramble function MainFlash memory Possible to set the validity/invalidity of the scramble Up to 1024 Kbytes function for the external areas 0x6000 0000 to Built-in Flash Accelerator System with 16 Kbytes trace 0xDFFF FFFF in 4 Mbytes units. buffer memory Possible to set two kinds of the scramble key The read access to Flash memory can be achieved without Note: It is necessary to prepare the dedicated software wait-cycle up to operation frequency of 72 MHz. Even at library to use the scramble function. the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash USB Interface Accelerator System. USB interface is composed of Device and Host. Security function for code protection WorkFlash memory USB device 32 Kbytes Read cycle: USB2.0 Full-Speed supported 6wait-cycle: the operation frequency more than 120 MHz, Max 6 Endpoint supported and up to 160 MHz Endpoint 0 is control transfer 4wait-cycle: the operation frequency more than 72 MHz, Endpoint 1, 2 can be selected Bulk-transfer, and up to 120 MHz Interrupt-transfer or Isochronous-transfer 2wait-cycle: the operation frequency more than 40 MHz, Endpoint 3 to 5 can select Bulk-transfer or and up to 72 MHz Interrupt-transfer 0wait-cycle: the operation frequency up to 40 MHz Endpoint 1 to 5 comprise Double Buffer Security function is shared with code protection The size of each endpoint is according to the follows. Endpoint 0, 2 to 5: 64 bytes Endpoint 1: 256 bytes Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04864 Rev. *D Revised September 25, 2017