MB9B610T Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9B610T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions 2 such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I C, LIN, Ethernet-MAC). The products which are described in this data sheet are placed into TYPE2 product categories inFM3 Family PERIPHERAL MANUA. Features 32-bit ARM Cortex -M3 Core External Bus Interface Processor version: r2p1 Supports SRAM, NOR and NAND Flash device Up to 144MHz Frequency Operation Up to 8 chip selects Memory Protection Unit (MPU): improves the reliability of an 8-/16-bit Data width embedded system Up to 25-bit Address bit Integrated Nested Vectored Interrupt Controller (NVIC): 1 Maximum area size : Up to 256 Mbytes NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels Supports Address/Data multiplex 24-bit System timer (Sys Tick): System timer for OS task Supports external RDY input management USB Interface (Max 2 channels) On-chip Memories USB interface is composed of Function and Host. PLL for USB is built-in, USB clock or Ethernet clock can be Flash memory generated by multiplication of Main clock. Up to 1 Mbyte USB function Built-in Flash Accelerator System with 16 Kbyte trace buffer USB2.0 Full-Speed supported memory The read access to Flash memory can be achieved without Max 6 EndPoint supported wait cycle up to operation frequency of EndPoint 0 is control transfer 72 MHz. Even at the operation frequency more than 72 MHz, EndPoint 1, 2 can be selected Bulk-transfer, an equivalent access to Flash memory can be obtained by Interrupt-transfer or Isochronous-transfer Flash Accelerator System. EndPoint 3 - 5 can be selected Bulk-transfer or Interrupt-transfer Security function for code protection EndPoint 1 to 5 is comprised Double Buffer EndPoint 0, 2 to 5:64 bytes SRAM EndPoint 1: 256 bytes This Series contain a total of up to 128 Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus USB host of Cortex-M3 core. SRAM1 is connected to System bus. USB2.0 Full/Low speed supported SRAM0 : Up to 64 Kbyte Bulk-transfer, interrupt-transfer and Isochronous-transfer SRAM1 : Up to 64 Kbyte support USB Device connected/dis-connected automatically detect IN/OUT token handshake packet automatically Max 256-byte packet-length supported Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04677 Rev.*A Revised April 1, 2016 MB9B610T Series 2 Ethernet - MAC (Max 2 channels) I C Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) Compliant with IEEE802.3 specification supported 10 Mbps / 100 Mbps data transfer rates supported DMA Controller (8 channels) MII/RMII for external PHY device supported. DMA Controller has an independent bus for CPU, so CPU and MII: Max 1channel DMA Controller can process simultaneously. RMII: Max 2hannels 8 independently configured and operated channels Full-Duplex and Half-Duplex mode supported. Transfer can be started by software or request from the Wake-ON-LAN supported built-in peripherals Built-in dedicated descriptor-system DMAC Transfer address area: 32-bit (4 Gbyte) Built-in 2 Kbyte Transmit FIFO and 2Kbyte Receive FIFO. Transfer mode: Block transfer/Burst transfer/Demand transfer Compliant IEEE1558-2008 (PTP) Transfer data type: byte/half-word/word Multi-function Serial Interface (Max 8 channels) Transfer block count: 1 to 16 4 channels with 16 steps9-bit FIFO (ch.4 to ch.7), 4 Number of transfers: 1 to 65536 channels without FIFO (ch.0 to ch.3) Operation mode is selectable from the followings for each A/D Converter (Max 32 channels) channel. UART 12-bit A/D Converter CSIO LIN Successive Approximation Register type 2 I C Built-in 3units Conversion time: 1.0 s 5 V UART Priority conversion available (priority at 2levels) Full-duplex double buffer Scanning conversion mode Selection with or without parity supported Built-in FIFO for conversion data storage (for SCAN Built-in dedicated baud rate generator conversion: 16 steps, for Priority conversion: 4 steps) External clock available as a serial clock Base Timer (Max 16 channels) Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) Operation mode is selectable from the followings for each channel. Various error detect functions available (parity errors, framing errors, and overrun errors) 16-bit PWM timer 16-bit PPG timer CSIO 16-/32-bit reload timer Full-duplex double buffer 16-/32-bit PWC timer Built-in dedicated baud rate generator Overrun error detect function available General Purpose I/O Port This series can use its pins as I/O ports when they are not used LIN for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral LIN protocol Rev.2.1 supported function can be allocated. Full-duplex double buffer Capable of pull-up control per pin Master/Slave mode supported Capable of reading pin level directly LIN break field generate (can be changed 13 to 16-bit length) Built-in the port relocate function LIN break delimiter generate (can be changed 1 to 4-bit Up 154 fast I/O Ports 176pin Package length) Some pin is 5 V tolerant I/O. Various error detect functions available (parity errors, framing SeePin Descriptio to confirm the corresponding pins. errors, and overrun errors) Document Number: 002-04677 Rev.*A Page 2 of 134