THIS SPEC IS OBSOLETE Spec No: 002-05629 Spec Title: MB9BD10T SERIES 32-BIT ARM(R) CORTEX(R)-M3 FM3 MICROCONTROLLER Replaced by: NONE MB9BD10T Series 32-bit Arm Cortex -M3 FM3 Microcontroller The MB9BD10T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the Arm Cortex -M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions 2 such as Motor Control Timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN, Ethernet-MAC). The products which are described in this datasheet are placed into TYPE 2 product categories inFM3 Family Peripheral Manua. Features USB device 32-bit Arm Cortex -M3 Core USB2.0 Full-Speed supported Processor version: r2p1 Max 6 EndPoint supported Up to 144 MHz Frequency Operation EndPoint 0 is control transfer EndPoint 1, 2 can be selected Bulk-transfer, Memory Protection Unit (MPU): improves the reliability of an Interrupt-transfer or Isochronous-transfer embedded system EndPoint 3 to 5 can be selected Bulk-transfer or Integrated Nested Vectored Interrupt Controller (NVIC): Interrupt-transfer 1 NMI (non-maskable interrupt) and 48 peripheral interrupts EndPoint 1 to 5 is comprised Double Buffers and 16 priority levels Endpoint 0, 2 to 5: 64 bytes 24-bit System timer (Sys Tick): System timer for OS task Endpoint 1: 256 bytes management USB host On-chip Memories USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer Flash memory support Up to 1 MB USB Device connected/dis-connected automatically detect Built-in Flash Accelerator System with 16 KB trace buffer IN/OUT token handshake packet automatically memory Max 256-byte packet-length supported The read access to Flash memory can be achieved without wait cycle up to operation frequency of 72 MHz. Even at the Wake-up function supported operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash CAN Interface (Max 2 channels) Accelerator System. Compatible with CAN Specification 2.0A/B Security function for code protection Maximum transfer rate: 1 Mbps SRAM Built-in 32 message buffer This Series contain a total of up to 128 KB on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Ethernet - MAC (Max 2 channels) Cortex-M3 core. SRAM1 is connected to System bus. Compliant with IEEE802.3 specification SRAM0: Up to 64 KB 10 Mbps / 100 Mbps data transfer rates supported SRAM1: Up to 64 KB MII/RMII for external PHY device supported. MII: Max 1 channel USB Interface (Max 2 channels) RMII: Max 2 channels USB interface is composed of Device and Host. Full-Duplex and Half-Duplex mode supported. PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main clock. Wake-ON-LAN supported Built-in dedicated descriptor-system DMAC Built-in 2 KB Transmit FIFO and 2 KB Receive FIFO. Compliant IEEE1588-2008 (PTP) PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main clock. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05629 Rev. *F Revised August 1, 2018