MB9DF126 MB9DF126B MB9DF126 Series Data Sheet Cortex R4 Family Cypress Cortex R4 Family CMOS MB9DF126 Series MB9DF126, MB9DF126B DESCRIPTION MB9DF126 series is based on Cypresss advanced ARM architecture (32-bit with instruction pipeline for RISC- like performance). Improvements compared to the previous generation include significantly improved perfor- mance at higher frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 128MHz operation frequency from an external resonator. Note: ARM, Cortex, Thumb and CoreSight are the trademarks of ARM Limited in the EU and other countries. Note: APIX is a registered mark of INOVA Semiconductors GmbH. TM Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: DS707-00002-4v1-E Revised November 4, 2015 MB9DF126 MB9DF126B REVISION HISTORY Version Date Remark 0.01 2010-08-12 Initial draft 0.02 2010-08-24 Updated according to latest short spec 0.03 2011-01-27 Updated Overview, Memory Map, Package and Pin Assignment, Interrupt/ DMA chapter with relavent information. Removed Recommended settings chapter. 0.04 2011-02-01 Updated Electrical characteristics chapter and modfied the document foot- er. 0.05 2011-02-04 Updated Block diagram with CRC, Overview, Table 2-1, Table 3-2, Table 4-1, Table 4-3, Table 6-1, Table 6-3, Figure 6-3, Table 6-4, Table 6-5, Table 6-9, Table 6-11, Table 6-14, Figure 6-8. Renamed Pnn m to Pi jj. 0.06 2011-02-15 Updated Document code. Updated Figure 3-2, Table 3-1, and Section 3.3.2 0.07 2011-03-10 Updated QFP-296 diagram, QFP-296 Package pinout table, Pin circuit type of QFP-296, I/O circuit types. 1.00 2011-03-18 Updated IO MAP. 1.01 2011-03-31 Updated Table 6-5 with PLL information and modified Table2-2. 1.02 2011-04-06 Updated Section I/O Pins and their functions and I/O Pin Types. 1.03 2011-05-04 Added RICFG information in Section 3.2.2. Added Procudures chapter. Re- named EEFLASH in Memory and Config(MEMORY CONFIG)AHB Bus Memory Map 1.04 2011-05-13 Renamed APIX power supply pins in QFP-296 Package diagram and QFP- 296 Package pinout table. 1.05 2011-05-27 Added Section Master ID. 1.06 2012-05-04 Added Input Level Description and Drive Strenght Information. Corrected IO circuit diagrams, ID value and reference supply in DC characrteristics. Added current consumption values 1.07 2012-07-02 Added handling devices, ordering information, flash programming times. 1.08 2012-07-10 Added RC Oscillator Frequency, modified Characteristics to match evalua- tion results. DMA channel registers limited to 8. 2.0 2012-08-21 No longer preliminary revision 2.1 2012-12-13 Trademark note added, Support note removed, package information updat- ed, std version for Warning, back cover changed, boundary scan chapter updated, new HSSPI timing, ADC reference values Document Number: DS707-00002-4v1-E Page ii