S6E2C1 Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2C1 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as 2 motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I C, LIN). The products that are described in this data sheet are placed into TYPE3-M4 product categoriesFM4 Family Peripheral Manual Main Part (002-04856) Features External Bus Interface Supports SRAM, NOR, NAND flash and SDRAM device 32-bit ARM Cortex-M4F Core Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) Processor version: r0p1 8-/16-/32-bit data width Up to 200 MHz frequency operation Up to 25-bit address bus FPU built-in Supports address/data multiplexing Support DSP instructions Supports external RDY function Memory protection unit (MPU): improves the reliability of an embedded system Supports scramble function Possible to set the validity/invalidity of the scramble Integrated nested vectored interrupt controller (NVIC): 1 NMI function for the external areas 0x6000 0000 to (non-maskable interrupt) and 128 peripheral interrupts and 0xDFFF FFFF in 4 Mbytes units. 16 priority levels Possible to set two kinds of the scramble key 24-bit system timer (Sys Tick): system timer for OS task Note: It is necessary to use the Cypress provided software management library to use the scramble function. On-chip Memories Multi-function Serial Interface (Max 16 Channels) Flash memory Separate 64 byte receive and transmit FIFO buffers for This series is based on two independent on-chip flash channels 0 to 7. memories. Operation mode is selectable for each channel from the Up to 2048 Kbytes following: Built-in flash accelerator system with 16 Kbytes trace buffer UART memory CSIO (SPI) Read access to flash memory that can be achieved without LIN 2 wait-cycle up to an operating frequency of 72 MHz. Even at I C the operating frequency more than 72 MHz, an equivalent single cycle access to flash memory can be obtained by UART the flash accelerator system. Full-duplex double buffer Security function for code protection Selection with or without parity supported Built-in dedicated baud rate generator SRAM External clock available as a serial clock This is composed of three independent SRAMs (SRAM0, Various error detect functions available (parity errors, SRAM1 and SRAM2). SRAM0 is connected to the I-code bus framing errors, and overrun errors) and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 CSIO (SPI) are connected to system bus of Cortex-M4F core. Full-duplex double buffer SRAM0: up to 192 Kbytes Built-in dedicated baud rate generator SRAM1: 32 Kbytes Overrun error detect function available SRAM2: 32 Kbytes Serial chip select function (ch 6 and ch 7 only) Supports high-speed SPI (ch 4 and ch 6 only) Data length 5 to 16-bit Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05032 Rev.*A Revised February 5, 2016 S6E2C1 Series LIN D/A Converter (Max two channels) LIN protocol Rev.2.1 supported R-2R type Full-duplex double buffer 12-bit resolution Master/slave mode supported LIN break field generation (can change to 13- to 16-bit length) Base Timer (Max 16 channels) LIN break delimiter generation (can change to 1- to 4-bit length) Operation mode is selected from the following for each Various error detect functions available (parity errors, channel: framing errors, and overrun errors) 2 16-bit PWM timer I C Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) 16-bit PPG timer supported 16-/32-bit reload timer Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported 16-/32-bit PWC timer DMA Controller (Eight Channels) General Purpose I/O Port This series can use its pins as general purpose I/O ports DMA controller has an independent bus, so the CPU and when they are not used for external bus or peripherals DMA controller can process simultaneously. moreover, the port relocate function is built in. It can set the Eight independently configured and operated channels I/O port to which the peripheral function can be allocated. Transfer can be started by software or request from the Capable of pull-up control per pin built-in peripherals Capable of reading pin level directly Transfer address area: 32-bit (4 GB) Built-in port-relocate function Transfer mode: Block transfer/Burst transfer/Demand transfer Up to 120 high-speed general-purpose I/O ports in 144-pin package Transfer data type: bytes/half-word/word Some pins 5 V tolerant I/O. Transfer block count: 1 to 16 See4. Pin Description and5. I/O Circuit Typ for the Number of transfers: 1 to 65536 corresponding pins. Multi-function Timer (Max three units) DSTC (Descriptor System Data Transfer Controller The multi-function timer is composed of the following blocks: 256 channels) The DSTC can transfer data at high-speed without going via Minimum resolution: 5.00 ns the CPU. The DSTC adopts the descriptor system and, 16-bit free-run timer 3 ch/unit following the specified contents of the descriptor that has Input capture 4 ch/unit already been constructed on the memory, can access directly Output compare 6 ch/unit the memory/peripheral device and perform the data-transfer A/D activation compare 6 ch/unit operation. Waveform generator 3 ch/unit It supports the software activation, the hardware activation, and the chain activation functions. 16-bit PPG timer 3 ch/unit The following functions can be used to achieve the motor control: A/D Converter (Max 32 Channels) PWM signal output function 12-bit A/D Converter DC chopper waveform output function Successive approximation type Built-in three units Dead time function Conversion time: 0.5 s at 5 V Input capture function Priority conversion available (priority at two levels) Scanning conversion mode A/D convertor activate function Built-in FIFO for conversion data storage (for SCAN DTIF (motor emergency stop) interrupt function conversion: 16 steps, for priority conversion: 4 steps) Document Number: 002-05032 Rev.*A Page 2 of 191