S6E2C3 Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2C3 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as 2 motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I C, LIN). The products that are described in this data sheet are placed into TYPE3-M4 product categoriesFM4 Family Peripheral Manual Main Part (002-04856) Features External Bus Interface 32-bit ARM Cortex-M4F Core Supports SRAM, NOR, NAND flash and SDRAM device Processor version: r0p1 Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) Up to 200 MHz frequency operation 8-/16-/32-bit data width FPU built-in Up to 25-bit address bus Support DSP instructions Supports address/data multiplexing Memory protection unit (MPU): improves the reliability of an Supports external RDY function embedded system Supports scramble function Integrated nested vectored interrupt controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and Possible to set the validity/invalidity of the scramble function 16 priority levels for the external areas 0x6000 0000 to 0xDFFF FFFF in 4 Mbytes units. 24-bit system timer (Sys Tick): system timer for OS task management Possible to set two kinds of the scramble key Note: It is necessary to use the Cypress provided software library to use the scramble function. On-chip Memories Flash memory USB Interface (Max two Channels) This series is based on two independent on-chip flash The USB interface is composed of a function and a host. memories. USB function Up to 2048 Kbytes USB 2.0 Full-speed supported Built-in flash accelerator system with 16 Kbytes trace buffer Max 6 EndPoint supported memory EndPoint 0 is control transfer Read access to flash memory that can be achieved without EndPoint 1, 2 can be selected bulk-transfer, wait-cycle up to an operating frequency of 72 MHz. Even at the operating frequency more than 72 MHz, an equivalent interrupt-transfer or isochronous-transfer single cycle access to flash memory can be obtained by EndPoint 3 to 5 can select bulk-transfer or the flash accelerator system. interrupt-transfer Security function for code protection EndPoint 1 to 5 comprise double buffer SRAM The size of each endpoint is as follows. This is composed of three independent SRAMs (SRAM0, Endpoint 0, 2 to 5: 64 byte SRAM1 and SRAM2). SRAM0 is connected to the I-code bus EndPoint 1: 256 byte or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are USB host connected to system bus of Cortex-M4F core. USB2.0 Full-Speed/Low-Speed supported SRAM0: up to 192 Kbytes Bulk-transfer, interrupt-transfer, and isochronous-transfer SRAM1: 32 Kbytes support SRAM2: 32 Kbytes USB Device connected/dis-connected automatically detect IN/OUT token handshake packet automatically Max 256-byte packet length supported Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04988 Rev.*A Revised February 5, 2016 S6E2C3 Series Multi-function Serial Interface (Max 16 channels) DSTC (Descriptor System data Transfer Controller 256 Channels) Separate 64 byte receive and transmit FIFO buffers for The DSTC can transfer data at high-speed without going via channels 0 to 7. the CPU. The DSTC adopts the descriptor system and, Operation mode is selectable for each channel from the following the specified contents of the descriptor that has following: UART already been constructed on the memory, can access directly CSIO (SPI) the memory/peripheral device and perform the data-transfer LIN operation. 2 I C It supports the software activation, the hardware activation, UART and the chain activation functions. Full-duplex double buffer Selection with or without parity supported A/D Converter (Max 32 channels) Built-in dedicated baud rate generator External clock available as a serial clock 12-bit A/D Converter Various error detect functions available (parity errors, Successive approximation type framing errors, and overrun errors) Built-in three units CSIO (SPI) Conversion time: 0.5 s at 5 V Full-duplex double buffer Priority conversion available (priority at two levels) Built-in dedicated baud rate generator Scanning conversion mode Overrun error detect function available Built-in FIFO for conversion data storage (for SCAN Serial chip select function (ch 6 and ch 7 only) conversion: 16 steps, for priority conversion: 4 steps) Supports high-speed SPI (ch 4 and ch 6 only) Data length 5 to 16-bit D/A Converter (Max 2 Channels) LIN R-2R type LIN protocol Rev.2.1 supported 12-bit resolution Full-duplex double buffer Master/slave mode supported Base Timer (Max 16 Channels) LIN break field generation (can change to 13- to 16-bit Operation mode is selected from the following for each length) LIN break delimiter generation (can change to 1- to 4-bit channel: length) 16-bit PWM timer Various error detect functions available (parity errors, framing errors, and overrun errors) 16-bit PPG timer 2 I C 16-/32-bit reload timer Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported 16-/32-bit PWC timer Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported General Purpose I/O Port This series can use its pins as general purpose I/O ports DMA Controller (Eight channels) when they are not used for external bus or peripherals DMA controller has an independent bus, so the CPU and moreover, the port relocate function is built in. It can set the DMA controller can process simultaneously. I/O port to which the peripheral function can be allocated. Eight independently configured and operated channels Capable of pull-up control per pin Transfer can be started by software or request from the Capable of reading pin level directly built-in peripherals Built-in port-relocate function Transfer address area: 32-bit (4 GB) Up to 120 high-speed general-purpose I/O ports in 144 pin Transfer mode: Block transfer/Burst transfer/Demand package transfer Some pins 5V tolerant I/O. Transfer data type: bytes/half-word/word See 4. Pin Descriptions and 5. I/O Circuit Type for the Transfer block count: 1 to 16 corresponding pins. Number of transfers: 1 to 65536 Document Number: 002-04988 Rev.*A Page 2 of 198