S6E2C5 Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2C5 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as 2 motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I C, LIN). The products that are described in this data sheet are placed into TYPE3-M4 product categoriesFM4 Family Peripheral Manual Main Part (002-04856) Features 32-bit ARM Cortex-M4F Core External Bus Interface Supports SRAM, NOR, NAND flash and SDRAM device Processor version: r0p1 Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) Up to 200 MHz frequency operation 8-/16-/32-bit data width FPU built-in Up to 25-bit address bus Support DSP instructions Supports address/data multiplexing Memory protection unit (MPU): improves the reliability of an Supports external RDY function embedded system Supports scramble function Integrated nested vectored interrupt controller (NVIC): 1 NMI Possible to set the validity/invalidity of the scramble function (non-maskable interrupt) and 128 peripheral interrupts and for the external areas 0x6000 0000 to 0xDFFF FFFF in 4 16 priority levels Mbytes units. 24-bit system timer (Sys Tick): system timer for OS task Possible to set two kinds of the scramble key management Note: It is necessary to use the Cypress provided software library to use the scramble function. On-chip Memories USB Interface (Max two Channels) Flash memory The USB interface is composed of a function and a host. This series is based on two independent on-chip flash memories. USB function USB 2.0 Full-speed supported Up to 2048 Kbytes Max 6 EndPoint supported Built-in flash accelerator system with 16 Kbytes trace buffer EndPoint 0 is control transfer memory EndPoint 1, 2 can be selected bulk-transfer, Read access to flash memory that can be achieved without wait-cycle up to an operating frequency of 72 MHz. Even at interrupt-transfer or isochronous-transfer the operating frequency more than 72 MHz, an equivalent EndPoint 3 to 5 can select bulk-transfer or single cycle access to flash memory can be obtained by interrupt-transfer the flash accelerator system. EndPoint 1 to 5 comprise double buffer Security function for code protection The size of each endpoint is as follows. SRAM Endpoint 0, 2 to 5: 64 byte This is composed of three independent SRAMs (SRAM0, EndPoint 1: 256 byte SRAM1 and SRAM2). SRAM0 is connected to the I-code bus USB host or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are USB2.0 Full-Speed/Low-Speed supported connected to system bus of Cortex-M4F core. Bulk-transfer, interrupt-transfer, and isochronous-transfer support SRAM0: up to 192 Kbytes USB Device connected/dis-connected automatically detect SRAM1: 32 Kbytes IN/OUT token handshake packet automatically SRAM2: 32 Kbytes Max 256-byte packet length supported Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04984 Rev.*A Revised February 8, 2016 S6E2C5 Series 2 I C CAN Interface (Max two Channels) Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) Compatible with CAN specification 2.0A/B supported Maximum transfer rate: 1 Mbps Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported Built-in 32-message buffer DMA Controller (Eight channels) CAN-FD Interface (One Channel) DMA controller has an independent bus, so the CPU and Compatible with CAN Specification 2.0A/B DMA controller can process simultaneously. Maximum transfer rate: 5 Mbps Eight independently configured and operated channels Message buffer for receiver: up to 192 messages Transfer can be started by software or request from the Message buffer for transmitter: up to 32 messages built-in peripherals CAN with flexible data rate (non-ISO CAN FD) Transfer address area: 32-bit (4 GB) Notes: Transfer mode: Block transfer/Burst transfer/Demand CAN FD cannot communicate between non-ISO CAN FD transfer and ISO CAN FD, because non-ISO CAN FD and ISO CAN FD are different frame format. Transfer data type: bytes/half-word/word About the problem ofnon-ISO CAN F, see the White Transfer block count: 1 to 16 Paper from CiA(CAN in Automation).