S6E2CC Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2CC Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as 2 motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I C, LIN). The products that are described in this data sheet are placed into TYPE3-M4 product categoriesFM4 Family Peripheral Manual Main Part (002-04856) Features External Bus Interface Supports SRAM, NOR, NAND flash and SDRAM device 32-bit ARM Cortex-M4F Core Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) Processor version: r0p1 8-/16-/32-bit data width Up to 200 MHz frequency operation Up to 25-bit address bus FPU built-in Supports address/data multiplexing Support DSP instructions Supports external RDY function Memory protection unit (MPU): improves the reliability of an embedded system Supports scramble function Possible to set the validity/invalidity of the scramble Integrated nested vectored interrupt controller (NVIC): 1 NMI function for the external areas 0x6000 0000 to (non-maskable interrupt) and 128 peripheral interrupts and 0xDFFF FFFF in 4 Mbytes units. 16 priority levels Possible to set two kinds of the scramble key 24-bit system timer (Sys Tick): system timer for OS task Note: It is necessary to use the Cypress provided software management library to use the scramble function. On-chip Memories USB Interface (Max two channels) The USB interface is composed of a function and a host. Flash memory This series is based on two independent on-chip flash USB function USB 2.0 Full-speed supported memories. Max 6 EndPoint supported Up to 2048 Kbytes EndPoint 0 is control transfer Built-in flash accelerator system with 16 Kbytes trace buffer memory EndPoint 1, 2 can be selected bulk-transfer, interrupt-transfer or isochronous-transfer Read access to flash memory that can be achieved without wait-cycle up to an operating frequency of 72 MHz. Even at EndPoint 3 to 5 can select bulk-transfer or the operating frequency more than 72 MHz, an equivalent interrupt-transfer single cycle access to flash memory can be obtained by EndPoint 1 to 5 comprise double buffer the flash accelerator system. The size of each endpoint is as follows. Security function for code protection Endpoint 0, 2 to 5: 64 byte EndPoint 1: 256 byte SRAM This is composed of three independent SRAMs (SRAM0, USB host SRAM1 and SRAM2). SRAM0 is connected to the I-code bus USB2.0 Full-Speed/Low-Speed supported and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 Bulk-transfer, interrupt-transfer, and isochronous-transfer support are connected to system bus of Cortex-M4F core. USB Device connected/dis-connected automatically detect SRAM0: up to 192 Kbytes IN/OUT token handshake packet automatically SRAM1: 32 Kbytes Max 256-byte packet length supported SRAM2: 32 Kbytes Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04980 Rev.*A Revised February 5, 2016 S6E2CC Series LIN break delimiter generation (can change to 1- to 4-bit CAN Interface (Max two channels) length) Compatible with CAN specification 2.0A/B Various error detect functions available (parity errors, framing errors, and overrun errors) Maximum transfer rate: 1 Mbps 2 I C Built-in 32-message buffer Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported CAN-FD Interface (One channel) Compatible with CAN Specification 2.0A/B Maximum transfer rate: 5 Mbps DMA Controller (Eight Channels) DMA controller has an independent bus, so the CPU and Message buffer for receiver: up to 192 messages DMA controller can process simultaneously. Message buffer for transmitter: up to 32 messages Eight independently configured and operated channels CAN with flexible data rate (non-ISO CAN FD) Transfer can be started by software or request from the Notes: built-in peripherals CAN FD cannot communicate between non-ISO CAN FD and ISO CAN FD, because non-ISO CAN FD and ISO Transfer address area: 32-bit (4 GB) CAN FD are different frame format. Transfer mode: Block transfer/Burst transfer/Demand About the problem ofnon-ISO CAN F, see the White transfer Paper from CiA(CAN in Automation).