S6E2DH Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2DH Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as 2 graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN). The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main Part (002-04856). Features External Bus Interface 32-bit ARM Cortex-M4F Core Supports SRAM, NOR, NAND Flash and SDRAM devices Processor version: r0p1 Up to two chip selects CS0 and CS8 (CS8 is only for Up to 160 MHz frequency operation SDRAM) Built-in FPU 8-/16-bit data width Supports DSP instructions Up to 25-bit address bit Memory Protection Unit (MPU): improves the reliability of an Maximum area size : Up to 256 Mbytes embedded system Supports address/data multiplexing Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts Supports external RDY function and 16 priority levels Supports the scramble function 24-bit system timer (Sys Tick): System timer for OS task Possible to set the validity/invalidity of the scramble management function for the external areas 0x6000 0000 to 0x7FFF FFFF in 4 Mbytes units. Possible to set two kinds of the scramble key. On-Chip Memories Note: It is necessary to prepare the dedicated software Flash memory library to use the scramble function. This series has on-chip flash memory with these features: 384 Kbytes USB Interface (One channel) Built-in Flash Accelerator System with 16 Kbytes trace A USB interface is composed of device and host. buffer memory USB device Security function for code protection USB2.0 Full-Speed supported Notes: Max 6 EndPoint supported The read access to flash memory can be achieved EndPoint 0 is for control transfer without wait-cycle up to operation frequency of 72 MHz. EndPoint 1, 2 can be selected for bulk-transfer, Even at the operation frequency more than 72 MHz, an interrupt-transfer or isochronous-transfer equivalent access to flash memory can be obtained by Flash Accelerator System. EndPoint 3 to 5 can select bulk-transfer or interrupt-transfer SRAM EndPoint 1 to 5 comprise the double buffer This is composed of two independent SRAMs (SRAM0 and The size of each endpoint is as follows. SRAM2). SRAM0 is connected to I-code bus and D-code bus Endpoint 0, 2 to 5: 64 bytes of Cortex-M4F core. SRAM2 is connected to the system bus of Cortex-M4F core. EndPoint 1: 256 bytes SRAM0: 32 Kbytes USB host SRAM2: 4 Kbytes USB2.0 Full-Speed / Low-Speed supported Bulk-transfer, interrupt-transfer and isochronous-transfer VRAM support This series is equipped with a SRAM for GDC. USB device connected/disconnected automatically detect Max 512 Kbytes In/out token handshake packet automatically accepted VFLASH Max 256-byte packet-length supported S6E2DH5GJA is equipped with a Flash for GDC. Wake-up function supported 2 Mbytes Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05038 Rev.*A Revised March 4, 2016 S6E2DH Series CAN-FD Interface (One channel) DMA Controller (Eight channels) The DMA controller has an independent bus for the CPU, so Compatible with CAN Specification 2.0A/B the CPU and the DMA controller can process simultaneously. Maximum transfer rate: 5 Mbps 8 independently configured and operated channels Message buffer for receiver: Up to 192 messages Transfer can be started by software or requested from the built-in peripherals Message buffer for transmitter: Up to 32 messages Transfer address area: 32-bit (4 Gbytes) CAN with flexible data rate (non-ISO CAN FD) Transfer mode: Block transfer/Burst transfer/Demand Notes: transfer CAN FD cannot communicate between non-ISO CAN FD and ISO CAN FD, because non-ISO CAN FD and ISO Transfer data type: bytes/half-word/word CAN FD are different frame format. Transfer block count: 1 to 16 About the problem ofnon-ISO CAN F, see the White Paper from CiA(CAN in Automation). Number of transfers: 1 to 65536