THIS SPEC IS OBSOLETE Spec No: 001-99444 Spec Title: S6E2GH Series 32-bit ARM(R) Cortex(R)-M4F, FM4 Microcontroller Replaced by: 001-98708 S6E2GH Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2GH Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as motor 2 control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I C, LIN). The products that are described in this data sheet are placed into TYPE5-M4 product categories FM4 Family Peripheral Manual Main Part (MN709-00001). Features Supports scramble function 32-bit ARM Cortex-M4F Core Possible to set the validity/invalidity of the scramble function for the external areas 0x6000 0000 to Processor version: r0p1 0xDFFF FFFF in 4 Mbytes units. Up to 180 MHz frequency operation Possible to set two kinds of the scramble key Note: It is necessary to use the Cypress provided software FPU built-in library to use the scramble function. Support DSP instructions USB Interface (Max two channels) Memory protection unit (MPU): improves the reliability of an The USB interface is composed of a Device and a Host. embedded system USB Device Integrated nested vectored interrupt controller (NVIC): 1 NMI USB 2.0 Full-speed supported (non-maskable interrupt) and 128 peripheral interrupts and Max 6 EndPoint supported 16 priority levels EndPoint 0 is control transfer 24-bit system timer (Sys Tick): system timer for OS task EndPoint 1, 2 can be selected bulk-transfer, management interrupt-transfer or isochronous-transfer EndPoint 3 to 5 can select bulk-transfer or On-chip Memories interrupt-transfer Flash memory EndPoint 1 to 5 comprise double buffer This series is on-chip flash memories. The size of each endpoint is as follows. Up to 1024 Kbytes Endpoint 0, 2 to 5: 64 byte Built-in flash accelerator system with 16 Kbytes trace buffer EndPoint 1: 256 byte memory USB Host Read access to flash memory that can be achieved without USB2.0 Full-Speed/Low-Speed supported wait-cycle up to an operating frequency of 72 MHz. Even at the operating frequency more than 72 MHz, an equivalent Bulk-transfer, interrupt-transfer, and isochronous-transfer single cycle access to flash memory can be obtained by support the flash accelerator system. USB Device connected/dis-connected automatically detect Security function for code protection IN/OUT token handshake packet automatically Max 256-byte packet length supported SRAM Wake-up function supported This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to the I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are CAN Interface (Max one channels) connected to system bus of Cortex-M4F core. Compatible with CAN specification 2.0A/B SRAM0: up to 128 Kbytes Maximum transfer rate: 1 Mbps SRAM1: 32 Kbytes SRAM2: 32 Kbytes Built-in 32-message buffer External Bus Interface Multi-function Serial Interface (Max 10 Channels) Supports SRAM, NOR, NAND flash and SDRAM device Separate 64 byte receive and transmit FIFO buffers for channels 1 and channels 4 to 7. Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) Operation mode is selectable for each channel from the 8-/16-/32-bit data width following: Up to 25-bit address bus UART CSIO (SPI) Supports address/data multiplexing LIN Supports external RDY function Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-99444 Rev.*B Revised November 18, 2016