THIS SPEC IS OBSOLETE Spec No: 001-98940 Spec Title: S6E2H1 SERIES 32-BIT ARM(R) CORTEX(R)- M4F, FM4 MICROCONTROLLER Replaced by: NONE S6E2H1 Series 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2H1 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. These series is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions 2 such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I C, LIN). Features SRAM0: Up to 32 Kbytes SRAM1: Up to 16 Kbytes 32-bit ARM Cortex-M4F Core SRAM2: Up to 16 Kbytes Processor version: r0p1 External Bus Interface Up to 160 MHz Frequency Operation FPU built-in Supports SRAM, NOR, NAND Flash and SDRAM device Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) Support DSP instruction 8-/16-bit Data width Memory Protection Unit (MPU): improves the reliability of an embedded system Up to 25-bit Address bit Integrated Nested Vectored Interrupt Controller (NVIC): 1 Supports Address/Data multiplex NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels Supports external RDY function 24-bit System timer (Sys Tick): System timer for OS task Supports scramble function management Possible to set the validity/invalidity of the scramble function for the external areas 0x6000 0000 to On-chip Memories 0xDFFF FFFF in 4 Mbytes units. Possible to set two kinds of the scramble key Flash memory Note: It is necessary to prepare the dedicated software These series are based on two independent on-chip Flash library to use the scramble function. memories. MainFlash memory Multi-function Serial Interface (Max 8 channels) Up to 512 Kbytes Built-in Flash Accelerator System with 16 Kbytes trace 64 bytes with FIFO (the FIFO step numbers are variable buffer memory depending on the settings of the communication mode or bit length.) The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Operation mode is selectable from the followings for each Even at the operation frequency more than 72 MHz, an channel. equivalent access to Flash memory can be obtained by UART Flash Accelerator System. CSIO Security function for code protection LIN WorkFlash memory 2 I C 32 Kbytes UART Read cycle: Full-duplex double buffer 6 wait-cycle: the operation frequency more than 120 Selection with or without parity supported MHz, and up to 160 MHz Built-in dedicated baud rate generator 4 wait-cycle: the operation frequency more than 72 MHz, External clock available as a serial clock and up to 120 MHz Hardware Flow control : Automatically control the 2 wait-cycle: the operation frequency more than 40 MHz, transmission by CTS/RTS (only ch.4) and up to 72 MHz Various error detect functions available (parity errors, 0 wait-cycle: the operation frequency up to 40 MHz framing errors, and overrun errors) Security function is shared with code protection CSIO SRAM Full-duplex double buffer This is composed of three independent SRAMs (SRAM0, Built-in dedicated baud rate generator SRAM1 and SRAM2). SRAM0 is connected to I-code bus or Overrun error detect function available D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are Serial chip select function (ch.6 and ch.7 only) connected to System bus of Cortex-M4F core. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98940 Rev.*C Revised May 25, 2017