S71KL256SC0BHB003 Infineon

S71KS512SC0 S71KL256SC0 SUPPLEMENT S71KL512SC0 HyperFlash and HyperRAM Multi-Chip Package 1.8V/3V HyperFlash and HyperRAM Multi-Chip Package 3 V Distinctive Characteristics HyperFlash and HyperRAM in Multi-Chip Package (MCP) Optional Signals 1.8V, 512 Mb HyperFlash and 64 Mbit HyperRAM Reset (S71KS512SC0) INT output to generate external interrupt 3.0V, 512 Mb HyperFlash and 64 Mbit HyperRAM Busy to Ready Transition (S71KL512SC0) RSTO Output to generate system level Power-On Reset 3.0V, 256 Mb HyperFlash and 64 Mbit HyperRAM (POR) (S71KL256SC0) User configurable RSTO Low period FBGA 24-ball, 6 8 1.0 mm package High Performance HyperBus Interface Double-Data Rate (DDR) 1.8V I/O, 12 bus signals Two data transfers per clock Differential clock (CK/CK ) Up to 166-MHz clock rate (333 MB/s) at 1.8V V CC 3.0V I/O, 11 bus signals Up to 100-MHz clock rate (200 MB/s) at 3.0V V CC Single ended clock (CK) Chip Select (CS ) 8-bit data bus (DQ 7:0 ) Read-Write Data Strobe (RWDS) Bidirectional Data Strobe/Mask Output at the start of all transactions to indicate refresh latency Output during read transactions as Read Data Strobe Input during write transactions as Write Data Mask (Hyper- RAM only) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-03902 Rev. *D Revised February 23, 2017S71KS512SC0 S71KL256SC0 SUPPLEMENT S71KL512SC0 Contents General Description .........................................................3 Ordering Part Numbers .................................................. 11 HyperBus MCP Family with HyperFlash Valid Combinations - Standard .................................. 11 and HyperRAM ............................................................3 Valid Combinations Automotive Grade / HyperBus MCP 3 V Signal Descriptions .........................4 AEC-Q100 .................................................................12 HyperBus MCP Block Diagram .......................................5 Document History Page ................................................. 13 Physical Interface .............................................................6 Sales, Solutions, and Legal Information ...................... 14 HyperBus MCP FBGA 24-Ball, Worldwide Sales and Design Support ....................... 14 5x5 Array Footprint ......................................................6 Products ....................................................................14 Physical Diagram ........................................................7 PSoC Solutions ...................................................... 14 Electrical Specifications ..................................................8 Cypress Developer Community ................................. 14 Absolute Maximum Ratings .........................................8 Technical Support ..................................................... 14 DC Characteristics ......................................................8 Document Number: 002-03902 Rev. *D Page 2 of 14