Dual Low Dropout Voltage Regulator TLE 4473 GV55-2 Features Stand-by output 190 mA 5 V 2% Main output: 300 mA, 5 V tracked to the stand-by output Low quiescent current consumption Disable function separately for both outputs Wide operation range: up to 42 V PG-DSO-12-11 Very low dropout voltage 2 independent reset circuits Watchdog Output protected against short circuit Wide temperature range: -40 C to 150 C Overtemperature protection Overload protection Green product (RoHS compliant) AEC qualified Functional Description The TLE 4473 is a monolithic integrated voltage regulator with two low dropout outputs, a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum of 190 mA. The stand-by regulator transforms an input voltage V in the range of 5.6 V I V 42 V to an output voltage of V = 5.0 V (2%). The main output is tracked to the I Q2 stand by output voltage and provides also 5 V. A versions of this device with 5 V/3.3 V and 5 V/2.6 V are also available, please refer to the data sheet TLE 4473 G V53/ TLE 4473 G V52. The Inhibit input INH1 disables the output Q1 only, whereas Inhibit input INH2 disables both, Q1 and Q2 output. The quiescent current then is 1 A. The TLE 4473 is designed to supply microprocessor systems and sensors under the severe conditions of automotive applications and therefore is equipped with additional protection functions against overload, short circuit and overtemperature. The device operates in the wide junction temperature range of -40 C to 150 C. Type Package Marking TLE 4473 GV55-2 PG-DSO-12-11 (RoHS compliant) TLE4473 GV55-2 Data Sheet 1 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 The device features a reset with adjustable power on delay for each of the outputs. In addition the output for the microcontroller supply comes up with a watchdog in order to supervise a connected microcontroller Reset and Watchdog Behavior The reset output RO2 is in high-state if the voltage on the delay capacitor C is greater D2 or equal V . The delay capacitor C is charged with the current I for output DU2 D2 DC2 voltages greater than the reset threshold V . If the output voltage gets lower than V RT2 RT2 (reset condition) a fast discharge of the delay capacitor C sets in and as soon as V D2 D2 gets lower than V the reset output RO2 is set to low-level. The time for the delay DL2 capacitor charge is the reset delay time. For the power-on case the charging process of C starts from 0 V, which leads to the equation: D2 C V D2 DU2 t = ----------------------------- (1) Do, n I DC2 for the power-on reset delay time. When the voltage on the delay capacitor has reached V and reset was set to high, the DU2 watchdog circuit is enabled and discharges C with the constant current I . D2 DD2 If there is no rising edge observed at the watchdog input, C will be discharge down to D2 V . Then reset output RO2 will be set to low and C will be charged again with the DL2 D2 current I until V reaches V and reset will be set high again. DC2 D2 DU2 If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge period C is charged again and the reset output stays high. After V has reached V , D2 D2 DU2 the periodical cycle starts again. The watchdog timing is shown in Figure 1. The maximum duration between two watchdog pulses corresponds to the minimum watchdog trigger time T . Higher WI,tr capacitances on pin D2 result in longer watchdog trigger times: T = 0.34 ms/nF C (2) WI,tr D2 max If the output voltage Q1 decreases below V (typ. 4.65 V), the external capacitor C RT1 D1 is discharged by the reset generator of the main output. If the voltage on this capacitor drops below V , a reset signal is generated on pin 2 (RO1). If the output voltage rises DL1 above the reset threshold, C will be charged with the constant current I . After the D1 DC1 power-on-reset time the voltage on the capacitor reaches V and the reset output will DU1 be set high again. The value of the power-on-reset time can be set within a wide range depending of the capacitance of C using the above given equation (1) analogous for D1 Q1. Data Sheet 2 Rev. 1.2, 2008-10-28