TLE9263-3BQXV33 System Basis Chip Mid-Range+ System Basis Chip Family Features Two integrated Low-Drop Voltage Regulators: Main regulator (5 V or 3.3 V up to 250 mA) and auxiliary regulator (5 V up to 100 mA) with off-board usage protection Voltage regulator (5 V, 3.3 V or 1.8 V) with external PNP transistor configurable for off-board usage or for load sharing 1 high-speed CAN transceiver supporting FD communication up to 5 Mbit/s featuring CAN Partial Networking & CAN FD tolerant mode according to ISO 11898-2:2016 & SAE J2284 2 LIN transceivers LIN 2.2/ISO 17987-4/SAE J2602 4 high-side outputs 7 typ., 2 HV GPIOs, 3 HV wake inputs Integrated fail-safe and supervision functions, e.g. fail-safe, watchdog, interrupt- and reset outputs 16-bit SPI for configuration and diagnostics Potential applications Body Control Modules (BMC), Passive keyless entry and start modules, Gateway applications Heating, ventilation and air conditioning (HVAC) Seat, roof, tailgate, trailer, door and other closure modules Light control modules Gear shifters and selectors Product validation Qualified for automotive applications. Product validation according to AEC-Q100/101. Description Body System IC with Integrated Voltage Regulators, Power Management Functions, HS-CAN Transceiver supporting CAN FD featuring Partial Networking (incl. FD Tolerant Mode) and Multiple LIN Transceiver. Featuring Multiple High-Side Switches and High-Voltage Wake Inputs. Type Package Marking TLE9263-3BQXV33 PG-VQFN-48-31 TLE9263-3BQXV33 Datasheet 1 Rev. 1.1 www.infineon.com 2019-09-27 TLE9263-3BQXV33 Table of Contents Features 1 Potential applications . 1 Product validation 1 Description 1 Table of Contents . 2 1 Overview 6 2 Block Diagram . 8 3 Pin Configuration . 9 3.1 Pin Assignment . 9 3.2 Pin Definitions and Functions . 10 3.3 Hints for Unused Pins 12 3.4 Hints for Alternate Pin Functions 12 4 General Product Characteristics . 13 4.1 Absolute Maximum Ratings . 13 4.2 Functional Range 15 4.3 Thermal Resistance 16 4.4 Current Consumption 17 5 System Features 22 5.1 Block Description of State Machine . 23 5.1.1 Device Configuration and SBC Init Mode . 24 5.1.1.1 Device Configuration . 24 5.1.1.2 SBC Init Mode . 27 5.1.2 SBC Normal Mode 28 5.1.3 SBC Stop Mode 29 5.1.4 SBC Sleep Mode . 30 5.1.5 SBC Restart Mode 31 5.1.6 SBC Fail-Safe Mode 32 5.1.7 SBC Development Mode 33 5.2 Wake Features 35 5.2.1 Cyclic Sense . 35 5.2.1.1 Configuration and Operation of Cyclic Sense . 36 5.2.1.2 Cyclic Sense in Low Power Mode 39 5.2.2 Cyclic Wake . 40 5.2.3 Internal Timer . 41 5.3 Supervision Features . 41 5.4 Partial Networking on CAN . 42 5.4.1 CAN Partial Networking - Selective Wake Feature . 42 5.4.2 SBC Partial Networking Function 43 5.4.2.1 Activation of SWK 44 5.4.2.2 Wake-up Pattern (WUP) 45 5.4.2.3 Wake-up Frame (WUF) . 45 5.4.2.4 CAN Protocol Error Counter . 46 5.4.3 Diagnoses Flags 47 Datasheet 2 Rev. 1.1 2019-09-27