TLF35584QVVS1XUMA1 Infineon

OPTIREG PMIC TLF35584 Functional Safety PMIC Features High efficient power management integrated circuit (PMIC) Serial step up and step down pre regulator for wide input voltage range from 3.0 to 40 V with full performance and low over all power loss Low drop post regulator 5.0 V/200 mA for communication supply (QCO) Low drop post regulator 5.0 V/600 mA (TLF35584QxVS1) or 3.3 V/600 mA (TLF35584QxVS2) for C supply (QUC) Voltage reference 5.0 V 1% for ADC supply, 150 mA current capability (QVR) Two trackers for sensor supply following voltage reference 150 mA current capability each (QT1 and QT2) Standby regulator 5.0 V/10 mA (TLF35584QxVS1) or 3.3 V/10 mA (TLF35584QxVS2) (QST) Provides enable, sync out signal and voltage monitoring for an optional external post regulator for core supply Independent voltage monitoring block and error pin monitoring Configurable window and functional watchdog Safe State Control with two safe state signals with programmable delay 16-bit SPI, interrupt and reset function PRO-SIL Features: - ISO 26262 compliant supporting up to ASIL-D - Safety Documentation (Safety Manual & Safety Analysis Summary Report) Green Product (RoHS compliant) Potential applications Electric Power Steering Battery Management Inverter Transmission Engine Management Domain Control Product validation Qualified for Automotive Applications. Product validation according to AEC-Q100/101. Device Overview Please read the Important Notice and Warnings at the end of this document Rev 1.0 www.infineon.com/OPTIREG-PMIC 2019-03-25 OPTIREG PMIC TLF35584 Functional Safety PMIC Description Description The OPTIREG PMIC TLF35584 is a high efficient Functional Safety PMIC (Power Management Integrated Circuit). Type Package TLF35584QVVS1 (5.0 V Variant) PG-VQFN-48 TLF35584QVVS2 (3.3 V Variant) PG-VQFN-48 TLF35584QKVS1 (5.0 V Variant) PG-LQFP-64 TLF35584QKVS2 (3.3 V Variant) PG-LQFP-64 Application Example LDO Stby VST QST 3.3V/5.0V 3.3V (5.0V) V STBY (as LDO C) WakeUp Timer ENA FRE Set fSTEPDOWN high/low by FRE: open/GND ENABLE (KL 15) ENABLE Logic WAK STU WAKE/INH Set STEPUP usage yes/no by STU: open/GND Comparator VS2 (PG-LQFP-64 only) V Bat (KL30) VS1 Internal Supply and Clock Feedback DRG RSH SW1 Step Up- Step down- V PREREG Regulator Regulator BSG SW2 (PG-LQFP-64 only) RSL PG1 Feedback PG2 Bandgap 1 for Regulators External FB1 switchmode V Core FB2 post V LDO C For C FB3 (PG-LQFP-64 only) regulator Bandgap 2 core supply FB4 (PG-LQFP-64 only) (optional) for Voltage Mon. SYN Sync Out Sync EVC Enable ext.Core sup Feedback Voltage Enable Reset Output ROT SEC Set ext SMPR yes/no by Monitoring/ Reset Control SEC: open/GND Reset Function VCI QUC 3.3V/5.0V V LDO C INTERRUPT INT INTERRUPT LDO C For C supply Generator 3.3V (5.0V) SQUC (PG-LQFP-64 only) CHIP SELECT SCS LDO Com QCO 5.0V CLOCK V LDO Com SCL 5.0V For communication supply (CAN/FlexRay) SPI DATA IN SPI SDI QT1 5.0V V TR1 DATA OUT SDO Tracker 1 For sensor supply 5.0V C SQT1 (PG-LQFP-64 only) QT2 5.0V V TR2 Trigger Tracker 2 WDI Window Functional For sensor supply - - 5.0V Watchdog Watchdog SQT2 (PG-LQFP-64 only) Series QVR 5.0V Volt Ref. Protection V Volt Ref 5.0V resistors Safe State /ErrorPin ERR Error SMU Monitoring Control MPS SS1 Safe State 1 Driver TLF35584 SS2 Safe State 2 Driver AG4 (signal delayed) (PG-LQFP-64 only) 3.3V e.g. 1.3V (5V) V LDO C V Core Note: The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Please contact us for additional supportive documentation. For further information you may contact