Cyclone V Device Overview 2016.06.10 Send Feedback CV-51001 Subscribe The Cyclone V devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements and the increasing bandwidth requirements for high-volume and cost-sensitive applications. Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitable for applications in the industrial, wireless and wireline, military, and automotive markets. Related Information Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters. Key Advantages of Cyclone V Devices Table 1: Key Advantages of the Cyclone V Device Family Advantage Supporting Feature Lower power consumption Built on TSMC s 28 nm low-power (28LP) process technology and includes an abundance of hard intellectual property (IP) blocks Up to 40% lower power consumption than the previous generation device Improved logic integration 8-input adaptive logic module (ALM) and differentiation capabil Up to 13.59 megabits (Mb) of embedded memory ities Variable-precision digital signal processing (DSP) blocks Increased bandwidth 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers capacity Hard memory controllers Hard processor system Tight integration of a dual-core ARM Cortex-A9 MPCore processor, (HPS) with integrated hard IP, and an FPGA in a single Cyclone V system-on-a-chip (SoC) ARM Cortex -A9 Supports over 128 Gbps peak bandwidth with integrated data coherency MPCore processor between the processor and the FPGA fabric 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as ISO trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance 9001:2008 of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any Registered products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134CV-51001 2 Summary of Cyclone V Features 2016.06.10 Advantage Supporting Feature Lowest system cost Requires only two core voltages to operate Available in low-cost wirebond packaging Includes innovative features such as Configuration via Protocol (CvP) and partial reconfiguration Summary of Cyclone V Features Table 2: Summary of Features for Cyclone V Devices Feature Description Technology TSMC s 28-nm low-power (28LP) process technology 1.1 V core voltage Packaging Wirebond low-halogen packages Multiple device densities with compatible package footprints for seamless migration between different device densities (1) RoHS-compliant and leaded options High-performance Enhanced 8-input ALM with four registers FPGA fabric Internal memory M10K10-kilobits (Kb) memory blocks with soft error correction code (ECC) blocks Memory logic array block (MLAB)640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory Variable-precision Native support for up to three signal processing precision DSP levels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same variable-precision DSP block 64-bit accumulator and cascade Embedded internal coefficient memory Embedded Hard IP Preadder/subtractor for improved efficiency blocks Memory controller DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support Embedded PCI Express (PCIe ) Gen2 and Gen1 (x1, x2, or x4) hard IP transceiver I/O with multifunction support, endpoint, and root port Clock networks Up to 550 MHz global clock network Global, quadrant, and peripheral clock networks Clock networks that are not used can be powered down to reduce dynamic power (1) Contact Altera for availability. Cyclone V Device Overview Altera Corporation Send Feedback