Enhanced Configuration (EPC) Devices Datasheet 2016.05.04 Send Feedback CF52002 Subscribe Supported Devices Table 1: Altera EPC Devices Device Memory Size (bits) On-Chip ISP Support Cascading Reprogram Operating Voltage Decompres Support mable (V) sion Support Recommend ed EPC4 4,194,304 Yes Yes No Yes 3.3 EPC8 8,388,608 Yes Yes No Yes 3.3 EPC16 16,777,216 Yes Yes No Yes 3.3 Features EPC devices offer the following features: Single-chip configuration solution for Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone , Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA), Mercury , Stratix II, and Stratix II GX devices Contains 4-, 8-, and 16-Mb flash memories for configuration data storage On-chip decompression feature almost doubles the effective configuration density Standard flash die and a controller die combined into single stacked chip package External flash interface supports parallel programming of flash and external processor access to unused portions of memory Flash memory block or sector protection capability using the external flash interface Supported in EPC4 and EPC16 devices Page mode support for remote and local reconfiguration with up to eight configurations for the entire system Compatible with Stratix series remote system configuration feature Supports byte-wide configuration mode fast passive parallel (FPP) with an 8-bit data output per DCLK cycle Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs Pin selectable 2-ms or 100-ms power-on reset (POR) time Configuration clock supports programmable input source and frequency synthesis 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as ISO trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance 9001:2008 of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any Registered products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134CF52002 2 Functional Description 2016.05.04 Multiple configuration clock sources supported (internal oscillator and external clock input pin) External clock source with frequencies up to 100 MHz Internal oscillator defaults to 10 MHz and you can program the internal oscillator for higher frequen cies of 33, 50, and 66 MHz Clock synthesis supported using user programmable divide counter Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA (UFBGA) packages Vertical migration between all devices supported in the 100-pin PQFP package Supply voltage of 3.3 V (core and I/O) Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification Supports ISP using Jam Standard Test and Programming Language (STAPL) Supports JTAG boundary scan The nINIT CONF pin allows private JTAG instruction to start FPGA configuration Internal pull-up resistor on the nINIT CONF pin always enabled User programmable weak internal pull-up resistors on nCS and OE pins Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines Standby mode with reduced power consumption Note: For more information about FPGA configuration schemes and advanced features, refer to the configuration chapter in the appropriate device handbook. Functional Description The Altera EPC device is a single device with high speed and advanced configuration solution for high- density FPGAs. The core of an EPC device is divided into two major blocksa configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more than one Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed using the external flash interface after the FPGA configuration is complete. Enhanced Configuration (EPC) Devices Datasheet Altera Corporation Send Feedback