EPCQ256SI16N Intel

Quad-Serial Configuration (EPCQ) Devices Datasheet Subscribe CF52012 2020.01.23 Send Feedback Latest document on the web: PDF HTMLContents Contents 1. Quad-Serial Configuration (EPCQ) Devices Datasheet.....................................................4 1.1. Supported Devices.................................................................................................4 1.2. Features...............................................................................................................5 1.3. Operating Conditions..............................................................................................5 1.3.1. Absolute Maximum Ratings......................................................................... 5 1.3.2. Recommended Operating Conditions............................................................ 6 1.3.3. DC Operating Conditions.............................................................................6 1.3.4. ICC Supply Current....................................................................................7 1.3.5. Capacitance.............................................................................................. 7 1.4. Memory Array Organization.....................................................................................7 1.4.1. Address Range for EPCQ16......................................................................... 8 1.4.2. Address Range for EPCQ32......................................................................... 9 1.4.3. Address Range for EPCQ64......................................................................... 9 1.4.4. Address Range for EPCQ128......................................................................11 1.4.5. Address Range for EPCQ256......................................................................13 1.4.6. Address Range for EPCQ512/A...................................................................16 1.5. Memory Operations..............................................................................................16 1.5.1. Timing Requirements................................................................................17 1.5.2. Addressing Mode..................................................................................... 17 1.6. Registers............................................................................................................ 17 1.6.1. Status Register........................................................................................17 1.6.2. Flag Status Register................................................................................. 26 1.6.3. Non-Volatile Configuration Register.............................................................27 1.7. Summary of Operation Codes................................................................................29 1.7.1. 4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h)........................30 1.7.2. Write Enable Operation (06h).................................................................... 31 1.7.3. Write Disable Operation (04h)................................................................... 31 1.7.4. Read Bytes Operation (03h)...................................................................... 32 1.7.5. Fast Read Operation (0Bh)........................................................................ 33 1.7.6. Extended Dual Input Fast Read Operation (BBh)...........................................33 1.7.7. Extended Quad Input Fast Read Operation (EBh)..........................................34 1.7.8. Read Device Identification Operation (9Fh)..................................................34 1.7.9. Write Bytes Operation (02h)......................................................................35 1.7.10. Extended Dual Input Fast Write Bytes Operation (D2h)................................36 1.7.11. Extended Quad Input Fast Write Bytes Operation (12h or 38h)..................... 36 1.7.12. Erase Bulk Operation (C7h)..................................................................... 37 1.7.13. Erase Sector Operation (D8h).................................................................. 38 1.7.14. Erase Subsector Operation...................................................................... 39 1.8. Power Mode........................................................................................................ 40 1.9. Timing Information.............................................................................................. 40 1.9.1. Write Operation Timing.............................................................................40 1.9.2. Read Operation Timing............................................................................. 42 1.10. Programming and Configuration File Support......................................................... 42 1.11. Pin Information..................................................................................................43 1.11.1. Pin-Out Diagram for EPCQ16 and EPCQ32 Devices......................................43 1.11.2. Pin-Out Diagram for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A Devices...44 1.11.3. EPCQ Device Pin Description....................................................................44 Quad-Serial Configuration (EPCQ) Devices Datasheet Send Feedback 2