IS25LE512M IS25WE512M 512Mb SERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC IS25LE512M IS25WE512M 512Mb S ERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI & Q UAD I/O QPI DTR INTERFACE WITH ON CHIP ECC FEATURES Industry Standard Serial Interface Low Power with Wide Temp. Ranges - Single Voltage Supply - IS25LE512M: 512Mbit/64Mbyte IS25LE: 2.30V to 3.60V, 133MHz (max) - IS25WE512M: 512Mbit/64Mbyte IS25WE: 1.70V to 1.95V - 3 or 4 Byte Addressing Mode - 13 mA Active Read Current - Supports Standard SPI, Fast, Dual, Dual - 21 A Standby Current I/O, Quad, Quad I/O, SPI DTR, Dual I/O - 1 A Deep Power Down DTR, Quad I/O DTR, and QPI - Temp Grades: - Software & Hardware Reset - Temp Grades: - Supports Serial Flash Discoverable Extended: -40C to +105C Auto Grade (A3): -40C to +125C Parameters (SFDP) Advanced Security Protection High Performance Serial Flash (SPI) - Software and Hardware Write Protection - 50MHz Normal Read - Advanced Sector/Block Protection - Up to133Mhz Fast Read: - Top/Bottom Block Protection 133MHz (max) for 3.0V, - Power Supply Lock Protection 112MHz (max) for 1.8V - 4x256 Byte Dedicated Security Area - Up to 66MHz DTR (Dual Transfer Rate) with OTP User-lockable Bits - Equivalent Throughput of 532 Mb/s - 128 bit Unique ID for Each Device - Selectable Dummy Cycles (Call Factory) - Configurable Drive Strength - Supports SPI Modes 0 and 3 (1) Industry Standard Pin-out & Packages - More than 100,000 Erase/Program Cycles (2) - M =16-pin SOIC 300mil - More than 100-year Data Retention (2) - L = 8-contact WSON 8x6mm - 1-bit ERROR Detection and Correction (2) - G = 24-ball TFBGA 6x8mm (4x6 ball array) per 64-bit boundary (with ECC) (2) - H = 24-ball TFBGA 6x8mm (5x5 ball array) Flexible & Efficient Memory Architecture Notes: - Chip Erase with Uniform Sector/Block 1. Call Factory for other package options available. (2) 2. For optional 512 Byte Page size with 256 KB Erase (4/32/64KB or 4/32/256 KB) Block size, see the Ordering Information. (2) - Program 1 to 256 or 512 Byte per Page - Program/Erase Suspend & Resume Efficient Read and Program modes - Low Instruction Overhead Operations - Continuous Read 8/16/32/64 Byte Burst Wrap - Selectable Burst Length - QPI for Reduced Instruction Overhead - Data Learning Pattern for training in DTR operation Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A2 11/18/2020