IS41C16100C IS41LV16100C 1Mx16 FEBRUARY 2012 16Mb DRAM WITH EDO PAGE MODE FEATURES DESCRIPTION TTL compatible inputs and outputs tristate I/O The ISSI IS41C16100C and IS41LV16100C are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Ac- Refresh Interval: cess Memories. These devices offer a cycle access called Auto refresh Mode: 1,024 cycles /16 ms Extended Data Out (EDO) Page Mode. EDO Page Mode allows 1,024 random accesses within a single row with RAS-Only, CAS-before-RAS (CBR), and Hidden access cycle time as short as 30 ns per 16-bit word. It is Self refresh Mode: 1,024 cycles /128 ms asynchronous, as it does not require a clock signal input JEDEC standard pinout to synchronize commands and I/O. Single power supply: These features make the IS41C/41LV16100C ideally suited 5V 10% (IS41C16100C) for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral 3.3V 10% (IS41LV16100C) applications that run without a clock to synchronize with Byte Write and Byte Read operation via two CAS the DRAM. o o Industrial Temperature Range: -40 C to +85 C The IS41C/41LV16100C is packaged in a 42-pin 400-mil SOJ and 400-mil 50/44 pin TSOP (Type II). KEY TIMING PARAMETERS Parameter -50 Unit Max. RAS Access Time (tcra ) 50 ns Max. CAS Access Time (tcca ) 14 ns Max. Column Address Access Time (taa ) 25 ns Min. EDO Page Mode Cycle Time (tpc ) 30 ns Min. Read/Write Cycle Time (trc ) 85 ns Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. C 02/16/2012IS41C16100C IS41LV16100C PIN CONFIGURATIONS 50(44)-Pin TSOP (Type II) 42-Pin SOJ VDD 1 42 GND VDD 1 44 GND I/O0 2 41 I/O15 I/O0 2 43 I/O15 I/O1 3 42 I/O14 I/O1 3 40 I/O14 I/O2 4 41 I/O13 I/O2 4 39 I/O13 I/O3 5 40 I/O12 I/O3 5 38 I/O12 VDD 6 39 GND VDD 6 37 GND I/O4 7 38 I/O11 I/O4 7 36 I/O11 I/O5 8 37 I/O10 I/O5 8 35 I/O10 I/O6 9 36 I/O9 I/O6 9 34 I/O9 I/O7 10 35 I/O8 NC 11 34 NC I/O7 10 33 I/O8 NC 11 32 NC NC 12 33 NC NC 12 31 LCAS NC 13 32 LCAS WE 13 30 UCAS WE 14 31 UCAS 29 RAS 14 OE RAS 15 30 OE NC 15 28 A9 NC 16 29 A9 NC 16 27 A8 NC 17 28 A8 27 A0 18 A7 A0 17 26 A7 A1 19 26 A6 A1 18 25 A6 A2 20 25 A5 A2 19 24 A5 A3 21 24 A4 A3 20 23 A4 VDD 22 23 GND VDD 21 22 GND PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vdd Power GND Ground NC No Connection 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. C 02/16/2012