IS41LV16105D 1Mx16 16Mb DRAM WITH FAST PAGE MODE MARCH 2020 FEATURES DESCRIPTION The ISSI IS41LV16105D is a 1,048,576 x 16-bit high-perfor- TTL compatible inputs and outputs tristate I/O mance CMOS Dynamic Random Access Memories. Fast Refresh Interval: Page Mode allows 1,024 random accesses within a single row 1,024 cycles/16 ms with access cycle time as short as 20 ns per 16-bit word. It is asynchronous, as it does not require a clock signal input to Refresh Mode: synchronize commands and I/O. RAS-Only, CAS-before-RAS (CBR), and Hidden These features make the IS41LV16105D ideally suited for JEDEC standard pinout high-bandwidth graphics, digital signal processing, high- performance computing systems, and peripheral applications Single power supply: that run without a clock to synchronize with the DRAM. 3.3V 10% The IS41LV16105D is packaged in a 400-mil 50/44-pin TSOP Byte Write and Byte Read operation via two CAS (Type II). o o Industrial Temperature Range -40 C to 85 C KEY TIMING PARAMETERS Parameter -50 Unit Max. RAS Access Time (trac) 50 ns Max. CAS Access Time (tcac) 13 ns Max. Column Address Access Time (taa) 25 ns Min. Fast Page Mode Cycle Time (tpc) 20 ns Min. Read/Write Cycle Time (trc) 84 ns Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. B 03/06/2020IS41LV16105D PIN CONFIGURATIONS 44(50)-Pin TSOP (Type II) VDD 1 44 GND I/O0 2 43 I/O15 I/O1 3 42 I/O14 I/O2 4 41 I/O13 I/O3 5 40 I/O12 VDD 6 39 GND I/O4 7 38 I/O11 I/O5 8 37 I/O10 I/O6 9 36 I/O9 I/O7 10 35 I/O8 NC 11 34 NC NC 12 33 NC NC 13 32 LCAS WE 14 31 UCAS RAS 15 30 OE NC 16 29 A9 NC 17 28 A8 A0 18 27 A7 A1 19 26 A6 A2 20 25 A5 A3 21 24 A4 VDD 22 23 GND PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vdd Power GND Ground NC No Connection 2 Integrated Silicon Solution, Inc. Rev. B 03/06/2020